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m68hc08 microcontrollers freescale.com mc68hc08as32 data sheet rev. 4.1 mc68hc08as32/d july 13, 2005

mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 3 mc68hc08as32 data sheet to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location.
data sheet mc68hc08as32 ? rev. 4.1 4 freescale semiconductor revision history date revision level description page number(s) july, 2003 4 formatted to current publication standards throughout figure 2-2. control, status, and data register ? updated figure to include reset values, page references, and corrected reset states for ddra 29 figure 3-3. adc status and control register (adscr) ? expanded definition of coco bit for clarity. 50 figure 5-2. cgm i/ o register summary ? updated figure to include reset values and page references 91 figure 13-3. sim i/o register summary ? updated figure to include reset values and page references 185 figure 16-2. break i/o register summary ? updated figure to include reset values and page references 252 figure 8-3. irq i/o register summary ? updated figure to include reset values and page references 129 figure 11-1. i/o port register summary ?updated figure to include reset values, page references, and corrected reset states for ddra 139 figure 11-3. data direction register a (ddra) ? corrected reset states 141 figure 11-17. port f data register (ptf) ? corrected figure title 152 section 15. timer interface (tim) ? timer discrepancies corrected throughout this section. 227 figure 12-2. sci i/o register summary ? updated figure to include reset values and page references 157 12.3.6 idle characters ? added note for clarity 161 figure 14-3. spi i/o register summary ? updated figure to include reset values and page references 205 figure 4-3. bdlc i/ o register summary ? updated figure to include reset values and page references 57 17.2 functional operating range ? corrected operating temperature range value 264 17.4 5.0-volt dc electr ical characteristics ? added maximum rating for v dd + v dda /v ddref supply current in stop mode at ?40 c to 125 c 265 18.4 64-pin quad fl at pack (case 840b) ? corrected diagram for case 840b 277 july 2005 4.1 updated to meet freescale identity guidelines throughout
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 5 data sheet ? mc68hc08as32 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . 45 section 4. byte data link controller-digital (bdlc-d) . . . . . . . . . . . . 55 section 5. clock generator m odule (cgm). . . . . . . . . . . . . . . . . . . . . . 89 section 6. computer operat ing properly (cop) . . . . . . . . . . . . . . . . 109 section 7. central processor un it (cpu) . . . . . . . . . . . . . . . . . . . . . . 113 section 8. external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 section 9. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . 133 section 10. mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 section 11. input/output (i/o) ports . . . . . . . . . . . . . . . . . . . . . . . . . . 139 section 12. serial communi cations interface (s ci). . . . . . . . . . . . . . 155 section 13. system integrat ion module (sim) . . . . . . . . . . . . . . . . . . 183 section 14. serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . 201 section 15. timer interface (tim). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 section 16. development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 section 17. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 263 section 18. ordering information and mechanical specifi cations . . . . . . . . . . . . . . . . . . . 275
data sheet mc68hc08as32 ? rev. 4.1 6 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 7 data sheet ? mc68hc08as32 table of contents section 1. gener al description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.5 analog power supply pin (v dda /v ddaref ) . . . . . . . . . . . . . . . . . . . 23 1.4.6 adc high reference pin (v refh ) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.7 analog ground pin (v ssa /v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.8 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . 23 1.4.9 port a input/output (i/o) pins (pta7?pt a0) . . . . . . . . . . . . . . . . . . 23 1.4.10 port b i/o pins (ptb7/atd7?ptb0/atd0) . . . . . . . . . . . . . . . . . . . 23 1.4.11 port c i/o pins (ptc4?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.12 port d i/o pins (ptd6/atd14/tclka?ptd0/atd8) . . . . . . . . . . . . 24 1.4.13 port e i/o pins (pte7/spsck?pte0/txd) . . . . . . . . . . . . . . . . . . . 24 1.4.14 port f i/o pins (ptf3/tch5?ptf0/tch2) . . . . . . . . . . . . . . . . . . . 24 1.4.15 j1850 transmit pin digital (bdtxd). . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.16 j1850 receive pin digital (bdrxd) . . . . . . . . . . . . . . . . . . . . . . . . . 24 section 2. memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 electrically erasable programmable ro m (eeprom) . . . . . . . . . . . . . 36 2.5.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.1.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.1.2 eeprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.5.1.3 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.5.1.4 eeprom redundant mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.1.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.1.6 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
data sheet mc68hc08as32 ? rev. 4.1 8 freescale semiconductor 2.5.1.7 eeprom non-volatile register and eeprom array configuration register . . . . . . . . . . . . . . 42 2.5.2 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.2.2 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 section 3. anal og-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.1 adc port i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3 conversion time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.4 continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6.1 adc analog power pin (v dda /v ddaref )/adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6.2 adc analog ground pin ( vssa )/adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6.3 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.7.3 adc input clock register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 section 4. byte data link controller-digital (bdlc-d) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3.1 bdlc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.1.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.1.2 reset mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.1.3 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1.4 bdlc wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1.5 bdlc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1.6 digital loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1.7 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 9 4.4 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4.1 rx digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4.1.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4.2 j1850 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4.3 j1850 vpw symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . . . . . . . . . . 67 4.4.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.3 rx and tx shadow registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.5.4 digital loopback multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.5.5 state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.5.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.5.2 receiving a message in block mode . . . . . . . . . . . . . . . . . . . . . . 74 4.5.5.3 transmitting a message in block mode . . . . . . . . . . . . . . . . . . . . 74 4.5.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.5.5 summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.6 bdlc cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.6.1 bdlc analog and roundtrip delay register . . . . . . . . . . . . . . . . . . 77 4.6.2 bdlc control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6.3 bdlc control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.6.4 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.6.5 bdlc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 section 5. clock g enerator module (cgm) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.2 phase-locked loop circuit (pll). . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.2.1 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.2.3 automatic and manual pll bandwidth modes . . . . . . . . . . . . . . . 93 5.3.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.2.5 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
data sheet mc68hc08as32 ? rev. 4.1 10 freescale semiconductor 5.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . 98 5.4.4 analog power pin (v dda /v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.6 crystal output frequency signal (cgmxclk). . . . . . . . . . . . . . . . . 98 5.4.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.8 cgm cpu interrupt (cgmint). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.5.2 pll bandwidth control register. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.5.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.7 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.8 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.9 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.9.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.9.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . 105 5.9.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.9.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 section 6. computer o perating properly (cop) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.4 internal reset resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.7 cops (cop short timeout). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.8 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 112
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 11 section 7. central processor un it (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.3.2 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 section 8. external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 section 9. low-volt age inhibit (lvi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.3.1 polled lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.3.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.3.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
data sheet mc68hc08as32 ? rev. 4.1 12 freescale semiconductor section 10. mask options 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 section 11. input/o utput (i/o) ports 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.2.1 port a data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.1 port c data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.6.1 port e data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.7 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.7.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.7.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 section 12. serial commun ications interface (sci) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.3.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.3.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.3.3 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.3.4 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.3.5 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.3.6 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.3.7 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.8 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.9 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.10 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.11 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.12 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 13 12.3.13 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.3.14 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.4 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.4.1 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.6 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.7.1 pte0/txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.7.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.8.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12.8.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 12.8.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.8.6 sci data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 12.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 section 13. system in tegration module (sim) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . 186 13.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . 186 13.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . 187 13.3 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.3.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . 188 13.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . 189 13.3.2.3 illegal opcode reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . 191 13.4.2 sim counter during stop mode recovery . . . . . . . . . . . . . . . . . . . 191 13.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.5.1 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 13.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 13.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
data sheet mc68hc08as32 ? rev. 4.1 14 freescale semiconductor 13.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . 195 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 13.7.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 13.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . 200 section 14. serial pe ripheral interface (spi) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.3 pin name and register name conventions . . . . . . . . . . . . . . . . . . . . . 203 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.4.1 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.4.2 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.5.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.5.2 transmission format when cpha = 0. . . . . . . . . . . . . . . . . . . . . . 207 14.5.3 transmission format when cpha = 1. . . . . . . . . . . . . . . . . . . . . . 209 14.5.4 transmission initiation lat ency . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.6.1 overflow error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.6.2 mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 14.8 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.10.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.11 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.12.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.12.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.12.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 14.13 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.13.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.13.2 spi status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . 223 14.13.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 15 section 15. timer interface (tim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.3.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.3.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.3.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.3.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . 235 15.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . 236 15.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.6 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.7.1 tim clock pin (ptd6/atd14/tclk) . . . . . . . . . . . . . . . . . . . . . . . 239 15.7.2 tim channel i/o pins (ptf3/tch5?ptf0/tch2 and pte3/tch1?pte2/tch0) . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.8.3 tim counter modulo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 15.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . 243 15.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 section 16. development support 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.1.1 flag protection during break interrupt s . . . . . . . . . . . . . . . . . . . 252 16.2.1.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.2.1.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.2.1.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.2.2 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . 253 16.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.2.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.2.3.2 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
data sheet mc68hc08as32 ? rev. 4.1 16 freescale semiconductor 16.3 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.3.1.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.3.1.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.3.1.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.3.1.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.3.1.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.3.1.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 section 17. electri cal specifications 17.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 17.2 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.4 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.5 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 17.6 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 17.7 5.0-vdc 10% serial peripheral interface (spi ) timing. . . . . . . . . . . . 267 17.8 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.9 cgm component information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.10 cgm acquisition/lock time information . . . . . . . . . . . . . . . . . . . . . . . 271 17.11 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.12 ram characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.13 eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.14 bdlc transmitter vpw symbol timings . . . . . . . . . . . . . . . . . . . . . . . 272 17.15 bdlc receiver vpw symbol timings . . . . . . . . . . . . . . . . . . . . . . . . . 273 17.16 bdlc transmitter dc electrical characteri stics . . . . . . . . . . . . . . . . . 274 17.17 bdlc receiver dc electrical characteristics . . . . . . . . . . . . . . . . . . . 274 section 18. ordering information and mechanical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.3 52-pin plastic leaded chip carrier package (case 778). . . . . . . . . . . 276 18.4 64-pin quad flat pack (case 840b) . . . . . . . . . . . . . . . . . . . . . . . . . . 277
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 17 data sheet ? mc68hc08as32 section 1. general description 1.1 introduction the mc68hc08as32 is a member of t he low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus ). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processo r unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 features features include: high-performance m68hc08 architecture fully upward-compatible object co de with m6805, m146805, and m68hc05 families 8.4-mhz internal bus frequency 32,256 bytes of read-only memory (rom) rom data security 512 bytes of on-chip electrically erasable programmable read-only memory (eeprom) 1024 bytes of on-chip random-access memory (ram) serial peripheral interface module (spi) serial communications interface module (sci) 16-bit, 6-channel timer interface module (tim) clock generator module (cgm) 8-bit, 15-channel analog-to-digital converter module (adc) sae j1850 byte data link cont roller digital module (bdlc-d) system protection features: ? computer operating properly (cop) with optional reset ? low-voltage detection with optional reset ? illegal opcode detection with optional reset ? illegal address detection with optional reset
data sheet mc68hc08as32 ? rev. 4.1 18 freescale semiconductor low-power design (fully stat ic with stop and wait modes) master reset pin and power-on reset features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications c language support 1.3 mcu bl ock diagram figure 1-1 shows the structure of the mc68hc08as32.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 19 figure 1-1. mcu block diagram for 52-pin plcc and 64-pin qfp break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
data sheet mc68hc08as32 ? rev. 4.1 20 freescale semiconductor 1.4 pin assignments figure 1-2 shows the 52-pin plasti c leaded chip carrier (plcc) assignments and figure 1-3 shows the 64-pin quad flat pack (qfp) assignments. figure 1-2. 52-pin plcc assignments (top view) pte5/miso pte4/ss pte6/mosi pte7/spsck v ss v dd pta0 pta1 pta2 pta3 pta4 pta5 pta6 ptb4/atd4 ptd3/atd11 ptd2/atd10 ptd1/atd9 ptd0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 46 34 bdrxd cgmxfc ptf3/tch5 ptf2/tch4 ptf1/tch3 ptf0/tch2 rst irq ptc4 bdtxd pte0/txd pte1/rxd pte2/tch0 pte3/tch1 v ssa /v refl v dda /v ddaref v refh ptd6/atd14/tclk ptd5/atd13 ptd4/atd12 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 45 44 43 42 41 40 39 38 37 36 35 7 6 5 4 3 2 1 52 51 50 49 48 47
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 21 figure 1-3. 64-pin qfp assignments (top view) nc cgmxfc ptb7/atd7 ptf3/tch5 ptf2/tch4 ptf1/tch3 ptf0/tch2 rst irq ptc4 bdrxd bdtxd nc pte0/txd pte1/rxd pte2/tch0 pte3/tch1 nc ptd3/atd11 ptd2/atd10 nc nc ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda v refh nc ptd6/atd14/tclk ptd5 /atd13 ptd4/ atd12 nc nc ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd nc nc nc pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 nc 48 49
data sheet mc68hc08as32 ? rev. 4.1 22 freescale semiconductor 1.4.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins plac e high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. v ss is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). (see section 14. serial peripheral interface (spi) .) note: v ss must be grounded for proper mcu operation. figure 1-4. power supply bypassing 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connec tions for the on-chip oscillator circuit. (see section 5. clock generator module (cgm) .) 1.4.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire sy stem. it is driven low when any internal reset source is asserted. (see section 13. system integration module (sim) for more information.) mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown r epresent typical applications.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 23 1.4.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. (see section 8. external interrupt (irq) .) 1.4.5 analog power supply pin (v dda /v ddaref ) v dda /v ddaref is the power supply pin for the analog portion of the chip. these modules are the analog-to-digital converte r (adc) and the clock generator module (cgm). (see section 5. clock generator module (cgm) and section 3. analog-to-digital converter (adc) .) 1.4.6 adc high reference pin (v refh ) v refh is the high reference voltage for all analog-to-digital conversions. (see section 3. analog-to-digital converter (adc) .) 1.4.7 analog ground pin (v ssa /v refl ) the v ssa /v refl analog ground pin is used only for the ground connections for the analog sections of the circuit and should be decoupled as per the v ss digital ground pin. the analog sections consist of a clock generator module (cgm) and an analog-to-digital converter (adc). v ssa /v refl is also the lower reference supply for the adc. (see section 5. clock generator module (cgm) and section 3. analog-to-digital converter (adc) .) 1.4.8 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capac itor connection for the cgm. (see section 5. clock generator module (cgm) .) 1.4.9 port a input/output (i/o) pins (pta7?pta0) pta7?pta0 are general-purpose bidirectional i/o port pins. (see section 11. input/output (i/o) ports .) 1.4.10 port b i/o pins (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (adc). (see section 3. analog-to-digital converter (adc) and section 11. input/output (i/o) ports .) 1.4.11 port c i/o pins (ptc4?ptc0) ptc4 ? ptc3 and ptc1 ? ptc0 are general-purpose bidirectional i/o port pins. ptc2/mclk is a special function port that shares its pin with the system clock. (see section 11. input/output (i/o) ports .)
data sheet mc68hc08as32 ? rev. 4.1 24 freescale semiconductor 1.4.12 port d i/o pins (ptd6/atd14/tclka?ptd0/atd8) port d is a 7-bit special function port that shares all of its pins with the analog-to-digital converter module (adc) and one of its pins with the timer interface module (tim). (see section 15. timer interface (tim) , section 3. analog-to-digital converter (adc) , and section 11. input/output (i/o) ports .) 1.4.13 port e i/o pins (pte7/spsck?pte0/txd) port e is an 8-bit special function port that shares two of its pins with the timer interface module (tim), four of its pins with the serial peripheral interface module (spi), and two of its pins with the se rial communication inte rface module (sci). (see section 12. serial communications interface (sci) , section 14. serial peripheral interface (spi) , section 15. timer interface (tim) , and section 11. input/output (i/o) ports .) 1.4.14 port f i/o pins (ptf3/tch5?ptf0/tch2) port f is a 4-bit special function port that shares all of its pins with the timer interface module (tim). (see section 15. timer interface (tim) and section 11. input/output (i/o) ports .) 1.4.15 j1850 transmit pin digital (bdtxd) bdtxd is a serial digital output data physical interface to the j1850. (see section 4. byte data link controller-digital (bdlc-d) .) 1.4.16 j1850 receive pin digital (bdrxd) bdrxd is a serial digital input data ph ysical interface from the j1850. (see section 4. byte data link controller-digital (bdlc-d) . table 1-1. external pins summary pin name function driver type hysteresis reset state pta7?pta0 general-purpose i/o dual state no input, hi-z ptb7/atd7?ptb0/atd0 general-purpose i/o adc channel dual state no input, hi-z ptc4?ptc3 general-purpose i/o dual state no input, hi-z ptc2/mclk general-purpose i/o, bus clock output dual state no input, hi-z ptc1?ptc0 general-purpose i/o dual state no input, hi-z ptd6/atd14/tclk general-purpose i/o adc channel/timer external input clock dual state no input, hi-z ptd5/atd13?ptd0/atd8 general-purpose i/o adc channel dual state no input, hi-z
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 25 pte7/spsck general-purpose i/o spi clock dual state open drain yes input, hi-z pte6/mosi general-purpose i/o spi data path dual state open drain yes input, hi-z pte5/miso general-purpose i/o spi data path dual state open drain yes input, hi-z pte4/ss general-purpose i/o spi slave select dual state yes input, hi-z pte3/tch1 general-purpose i/o timer channel 1 dual state yes input, hi-z pte2/tch0 general-purpose i/o timer channel 0 dual state yes input, hi-z pte1/rxd general-purpose i/o sci receive data dual state yes input, hi-z pte0/txd general-purpose i/o sci transmit data dual state yes input, hi-z ptf3/tch5 general-purpose i/o timer channel 5 dual state yes input, hi-z ptf2/tch4 general-purpose i/o timer channel 4 dual state yes input, hi-z ptf1/tch3 general-purpose i/o timer channel 3 dual state yes input, hi-z ptf0/tch2 general-purpose i/o timer channel 2 dual state yes input, hi-z v dd chip power supply n/a n/a n/a v ss chip ground n/a n/a n/a v dda /v ddaref analog power supply (cgm and adc) n/a n/a n/a v ssa /v refl analog ground a/d reference voltage n/a n/a n/a v refh a/d reference voltage n/a n/a n/a osc1 external clock in n/a n/a input, hi-z osc2 external clock out n/a n/a output cgmxfc pll loop filter cap n/a n/a n/a irq external interrupt request n/a n/a input, hi-z rst reset n/a n/a output low bdrxd bdlc-d serial input n/a no input, hi-z bdtxd bdlc-d serial output output no output low table 1-1. external pins summary (continued) pin name function driver type hysteresis reset state
data sheet mc68hc08as32 ? rev. 4.1 26 freescale semiconductor table 1-2. clock source summary module clock source adc cgmxclk or bus clock bdlc cgmxclk cop cgmxclk cpu bus clock eeprom internal rc oscillator or bus clock spi bus clock/spsck sci cgmxclk tim bus clock or ptd6/atd14/tclk sim cgmout and cgmxclk irq bus clock brk bus clock lvi bus clock cgm osc1 and osc2
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 27 data sheet ? mc68hc08as32 section 2. memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 32,256 bytes of user rom 1024 bytes of ram 512 bytes of eeprom 36 bytes of user-defined vectors 224 bytes of monitor rom these definitions apply to the memory map representation of reserved and unimplemented locations. reserved ? accessing a reserved location can have unpredictable effects on mcu operation. unimplemented ? accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled 2.2 input/output (i/o) section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00, sim break status register, sbsr $fe01, sim reset status register, srsr $fe03, sim break flag control register, sbfcr $fe0c and $fe0d, break address registers, brkh and brkl $fe0e, break status and control register, brkscr $fe0f, lvi status register, lvisr $fe1c, eeprom non-vol atile register, eenvr $fe1d, eeprom control register, eecr $fe1f, eeprom array config uration register, eeacr $ffff, cop control register, copctl table 2-1 is a list of vector locations.
data sheet mc68hc08as32 ? rev. 4.1 28 freescale semiconductor . $0000 $003f i/o registers ? 58 bytes ($000a, $000b, $000e , $000f, $001b, a nd $0021 are reserved) $0040 $004f unimplemented 16 bytes $0050 $044f ram 1024 bytes $0450 $0451 reserved 2 bytes $0452 $07ff unimplemented 942bytes $0800 $09ff eeprom 512 bytes $0a00 $0a01 reserved 2 bytes $0a02 $7fff unimplemented 30,206 bytes $8000 $fdff rom 32,256 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f lvi status register (lvisr) $fe10 $fe1b reserved 12 bytes $fe1c eeprom non-volatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array config uration register (eeacr) $fe20 $feff monitor rom 224 bytes $ff00 $ffdb unimplemented 220 bytes $ffdc $ffff interrupt and reset vectors 36 bytes figure 2-1. memory map
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 29 addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 140. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 142. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 144. read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r r reset: unaffected by reset $0003 port d data register (ptd) see page 146. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r reset: unaffected by reset $0004 data direction register a (ddra) see page 141. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 143. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 145. read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r r reset: 0 0 0 0 0 0 0 0 $0007 data direction register d (ddrd) see page 147. read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 write: r reset: 0 0 0 0 0 0 0 0 $0008 port e data register (pte) see page 149. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 151. read: 0 0 0 0 ptf3 ptf2 ptf1 ptf0 write: r r r r reset: unaffected by reset $000a $000b reserved rrr r rrrr $000c data direction register e (ddre) see page 150. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 1 of 6)
data sheet mc68hc08as32 ? rev. 4.1 30 freescale semiconductor $000d data direction register f (ddrf) see page 153. read: 0 0 0 0 ddrf3 ddrf2 ddrf1 ddrf0 write: r r r r reset: 0 0 0 0 0 0 0 0 $000e $000f reserved rrr r rrrr $0010 spi control register (spcr) see page 221. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0011 spi status and control register (spscr) see page 223. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0012 spi data register (spdr) see page 225. read:r7r6r5 r4 r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 sci control register 1 (scc1) see page 170. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 172. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 174. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 175. read: scte tc scrf idle or nf fe pe write:rrr r rrrr reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 178. read: 0 0 0 0 0 0 bkf rpf write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 179. read:r7r6r5 r4 r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 179. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 2 of 6)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 31 $001a irq status and control register (iscr) see page 132. read: 0 0 0 0 irqf 0 imask mode1 write: r r r r r ack1 reset: 0 0 0 0 0 0 0 0 $001b reserved r r r r r r r r $001c pll control register (pctl) see page 99. read: pllie pllf pllon bcs 1111 write: r rrrr reset: 0 0 1 0 1 1 1 1 $001d pll bandwidth control register (pbwc) see page 100. read: auto lock acq xld 0000 write: r rrrr reset: $001e pll programming register (ppg) see page 102. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 0 0 0 0 0 0 0 $001f mask option register (mor) read: lvistop romsec lvirst lvipwr ssrec cops stop copd write:rrr r rrrr reset: 0 1 1 0 0 1 1 0 $0020 timer status and control register (tsc) see page 241. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0021 reserved r r r r r r r r $0022 timer counter register high (tcnth) see page 242. read: bit 15 14 13 12 11 10 9 bit 8 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0023 timer counter register low (tcntl) see page 242. read: bit 7 6 5 4 3 2 1 bit 0 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0024 timer modulo register high (tmodh) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0025 timer modulo register low (tmodl) see page 243. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0026 timer channel 0 status and control register (tsc0) see page 244. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 3 of 6)
data sheet mc68hc08as32 ? rev. 4.1 32 freescale semiconductor $0027 timer channel 0 register high (tch0h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 timer channel 0 register low (tch0l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0029 timer channel 1 status and control register (tsc1) see page 244. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $002a timer channel 1 register high (tch1h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b timer channel 1 register low (tch1l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002c timer channel 2 status and control register (tsc2) see page 244. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $002d timer channel 2 register high (tch2h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer channel 2 register low (tch2l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002f timer channel 3 status and control register (tsc3) see page 244. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $0030 timer channel 3 register high (tch3h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer channel 3 register low (tch3l see page 248. ) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0032 timer channel 4 status and control register (tsc4) see page 244. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 0 0 0 0 0 0 0 0 $0033 timer channel 4 register high (tch4h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 4 of 6)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 33 $0034 timer channel 4 register low (tch4l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0035 timer channel 5 status and control register (tsc5) see page 244. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset: 0 0 0 0 0 0 0 0 $0036 timer channel 5 register high (tch5h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer channel 5 register low (tch5l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0038 analog-to-digital status and control register (adscr) see page 50. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset: 0 0 0 1 1 1 1 1 $0039 analog-to-digital data register (adr) see page 52. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrr r rrrr reset: unaffected by reset $003a analog-to-digital input clock register (adiclk) see page 52. read: adiv2 adiv1 adiv0 adiclk 0000 write: rrrr reset: 0 0 0 0 0 0 0 0 $003b bdlc analog and roundtrip delay register (bard) see page 77. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset: 1 1 0 0 0 1 1 1 $003c bdlc control register 1 (bcr1) see page 78. read: imsg clks r1 r0 00 ie wcm write: r r reset: 1 1 1 0 0 0 0 0 $003d bdlc control register 2 (bcr2) see page 80. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset: 1 1 0 0 0 0 0 0 $003e bdlc state vector register (bsvr) see page 85. read: 0 0 i3 i2 i1 i0 0 0 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $003f bdlc data register (bdr) see page 87. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: unaffected by reset $fe00 sim break status register (sbsr) see page 198. read: r r r r r r sbsw r write: reset: 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 5 of 6)
data sheet mc68hc08as32 ? rev. 4.1 34 freescale semiconductor $fe01 sim reset status register (srsr) see page 199. read: por pin cop ilop ilad 0 lvi 0 write:rrr r rrrr reset: 1 0 0 0 0 0 0 0 $fe03 sim break flag control register (sbfcr) see page 200. read: bcferr r rrrr write: reset: 0 $fe07 reserved r r r r r r r r $fe0c break address register high (brkh) see page 254. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $fe0d break address register low (brkl) see page 254. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $fe0e break status and control register (brkscr) see page 253. read: brke brka 000000 write: r r rrrr reset: 0 0 0 0 0 0 0 0 $fe0f lvi status register (lvisr) see page 135. read: lviout 0 0 0 0 0 0 0 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $fe1c eeprom non-vola tile register (eenvr) see page 42. read: eera r r r eebp3 eebp2 eebp1 eebp0 write: reset: pv pv pv pv pv pv = programmed value or 1 in the erased state $fe1d eeprom control register (eecr) see page 40. read: eebclk 0 eeoff eeras1 eeras0 eelat 0 eepgm write: r r reset: 0 0 0 0 0 0 0 0 $fe1e reserved r r r r r r r r $fe1f eeprom array control register (eeacr) see page 42. read: eera r r r eebp3 eebp2 eebp1 eebp0 write:rrr r rrrr reset: eenvr eenvr eenvr eenvr eenvr $ffff cop control register (copctl) see page 111. read: low byte of reset vector write: clear cop counter reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected figure 2-2. control, status, and data register (sheet 6 of 6)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 35 table 2-1. vector addresses address vector $ffdc bdlc vector (high) $ffdd bdlc vector (low) $ffde adc vector (high) $ffdf adc vector (low) $ffe0 sci transmit vector (high) $ffe1 sci transmit vector (low) $ffe2 sci receive vector (high) $ffe3 sci receive vector (low) $ffe4 sci error vector (high) $ffe5 sci error vector (low) $ffe6 spi transmit vector (high) $ffe7 spi transmit vector (low) $ffe8 spi receive vector (high) $ffe9 spi receive vector (low) $ffea tim overflow vector (high) $ffeb tim overflow vector (low) $ffec tim channel 5 vector (high) $ffed tim channel 5 vector (low) $ffee tim channel 4 vector (high) $ffef tim channel 4 vector (low) $fff0 tim channel 3 vector (high) $fff1 tim channel 3 vector (low) $fff2 tim channel 2 vector (high) $fff3 tim channel 2 vector (low) $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) $ffff reset vector (low) low high priority
data sheet mc68hc08as32 ? rev. 4.1 36 freescale semiconductor 2.3 random-access memory (ram) addresses $0050?$044f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer al lows the stack to be anywhere in the 1024-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locati ons can be used for input/output (i/o) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m68hc05, m6805, and m146805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.4 read-only memory (rom) the user rom consists of 32,256 byte s of rom from addresses $8000?$fdff. the monitor rom and vectors are located from $fe20?$feff. see figure 2-1. memory map . thirty-six of the user vectors, $ffdc? $ffff, are dedicated to user-defined reset and interrupt vectors. security has been incorporated into the mc68hc08as32 to prevent external viewing of the rom contents. this f eature ensures that customer-developed software remains proprietary. 2.5 electrically erasable programm able rom (eeprom) this subsection describes the 512 bytes of electric ally erasable programmable rom (eeprom). features include: byte, block, or bulk erasable non-volatile redundant array option non-volatile block protection option non-volatile mcu configuration bits on-chip charge pump for programming/erasing
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 37 2.5.1 functional description addresses $0800?$09ff are eepr om locations. the 512 bytes of eeprom can be programmed or erased without an ex ternal voltage supply. the eeprom has a lifetime of 10,000 write-erase cycles in the non-redundant mode. reliability (data retention) is further ext ended if the redundanc y option is select ed. eeprom cells are protected with a non-volatile, 128-byte, block protection option. these options are stored in the eeprom non-volatile re gister (eenvr) and are loaded into the eeprom array configuration register (eeacr) after reset or a read of eenvr. the eeprom array also can be disabled to reduce current. 2.5.1.1 eeprom programming the unprogrammed state is a logic 1. progra mming changes the state to a logic 0. only valid eeprom bytes in the non- protected blocks and eenvr can be programmed. when the array is configured in the redundant mode, programming the first 256 bytes ($0800?$08ff) will also program the last 256 bytes ($0900?$09ff) with the same data. programming the eeprom in the non-redundant mode is recommended. program the data to both locations before entering the redundant mode. follow this procedure to program a byte of eeprom. refer to 17.4 5.0-volt dc electrical characteristics for timing values. 1. clear eeras1 and eeras0 and set eelat in the eecr ($fe1d). set value of t eepgm . (see notes a and b.) 2. write the desired data to any user eeprom address. 3. set the eepgm bit. (see note c.) 4. wait for a time, t eepgm , to program the byte. 5. clear the eepgm bit. 6. wait for the programming voltage time to fall, t eefpv . 7. clear eelat bits. (see note d.) 8. repeat steps 1 through 7 for more eeprom programming. notes: a. eeras1 and eeras0 must be cleared for programming. otherwise, you will be in erase mode. b. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom address will be latch ed. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. any attempts to read other eeprom data will read the latched data. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. c. the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. this is to ensure proper programming sequence. when eepgm is set, the on-board charge
data sheet mc68hc08as32 ? rev. 4.1 38 freescale semiconductor pump generates the program voltage and applies it to the user eeprom array. when the eepgm bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off. d. any attempt to clear both eepgm and eelat bits with a single instruction will clear only eepgm to allow time for removal of high voltage from the eeprom array. 2.5.1.2 eeprom erasing the unprogrammed state is a logic 1. only the valid eeprom bytes in the non-protected blocks and eenvr can be er ased. when the array is configured in the redundant mode, erasing the first 25 6 bytes ($0800?$08ff) also will erase the last 256 bytes ($0900?$09ff). follow this procedure to erase eeprom. refer to for timing values. 1. clear/set eeras1 and eeras0 to select byte/block/bulk erase, and set eelat in eectl. set value of t eebyt /t eeblock /t eebulk . (see note a.) 2. write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. set the eepgm bit. (see note b.) 4. wait for a time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for the erasing voltage time to fall, t eefpv . 7. clear eelat bits. (see note c.) 8. repeat steps 1 through 7 for mo re eeprom byte/block erasing. eebpx bit must be cleared to erase eep rom data in the co rresponding block. if any eebpx is set, the corresponding block cannot be erased an d bulk erase mode does not apply. notes: a. setting the eelat bit configures the address and data buses to latch data for erasing the array. only valid eeprom addresses with their data will be latched. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. in block erase mode, any eepr om address in the block can be used in step 2. all locations within this block will be erased. in bulk erase mode, any eeprom address can be used to erase the whole eeprom. eenvr is not affected with block or bulk erase. any attempts to read other eeprom data will read the latched data. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. b. to ensure the proper erasing s equence, the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. once eepgm is set, the type of erase mode cannot be modified. if eepgm is set, the on-board charge pum p generates the erase voltage
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 39 and applies it to the user eeprom array. when the eepgm bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. any attempt to clear both eepgm and eelat bits with a single instruction will clear only eepgm to allow time for removal of high voltage from the eeprom array. in general, all bits should be erased before being programmed. however, if program/erase cycling is of concern, th e following procedure can be used to minimize bit cycling in each eeprom byte . if any bit in a byte must be changed from a 0 to a 1, the byte needs to be erased before programming. table 2-2 summarizes the conditions for erasing before programming. 2.5.1.3 eeprom block protection the 512 bytes of eeprom are divided into four 128-byte blocks. each of these blocks can be protected separately by the eebpx bit. any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. table 2-3 shows the address ranges within the blocks. if the eebpx bit is set, that corresponding add ress block is protected. these bits are effective after a reset or a read to the eenvr register. the block protect configuration can be modified by erasing/ programming the corresponding bits in the eenvr register and then reading the eenvr register. in redundant mode, eebp3 and ee bp2 will have no meaning. table 2-2. eeprom program/erase cycling reduction eeprom data to be programmed eeprom data before programming erase before programming? 00 no 01 no 10 yes 11 no table 2-3. eeprom array address blocks block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff
data sheet mc68hc08as32 ? rev. 4.1 40 freescale semiconductor 2.5.1.4 eeprom redundant mode to extend the eeprom data retention, the array can be placed in redundant mode. in this mode, the first 256 bytes of user eeprom array are mapped to the last 256 bytes. reading, pr ogramming and erasing of t he first 256 eeprom bytes ($0800?$08ff) will physically affect two bytes of eeprom. addressing the last 256 bytes will not be recognized. bloc k protection still applies but eebp3 and eebp2 are meaningless. note: before entering redundant mode, prog ram the eeprom in non-redundant mode. 2.5.1.5 eeprom configuration the eeprom non-volatile register (eenvr ) contains configurations concerning block protection and redundancy. eenvr is physically located on the bottom of the eeprom array. the contents are non-volatile and are not modified by reset. on reset, this special register loads the eepr om configuration into a corresponding volatile eeprom array configuration regist er (eeacr). thereafter, all reads to the eenvr will reload eeacr. the eeprom configuration can be chang ed by programming/erasing the eenvr like a normal eeprom byte. the new array configuration will take effect with a system reset or a read of the eenvr. 2.5.1.6 eeprom control register this read/write register controls programming/erasing of the array. eebclk ? eeprom bus clock enable bit this read/write bit determines which cl ock will be used to drive the internal charge pump for programming/erasing. reset clears this bit. 1 = bus clock drives charge pump. 0 = internal rc oscillator drives charge pump. note: use the internal rc oscillator for applications in the 3- to 5-v range. address: $fe1d bit 7654321bit 0 read: eebclk 0 eeoff eeras1 eeras0 eelat 0 eepgm write: r r reset:00000000 r= reserved figure 2-3. eeprom control register (eecr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 41 eeoff ? eeprom power down bit this read/write bit disables the eeprom module for lower power consumption. any attempts to access the array will give unpredictable results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array note: the eeprom requires a recovery time, t eeoff , to stabilize after clearing the eeoff bit. refer to for timing values. eeras1?eeras0 ? eeprom erase bits these read/write bits set the programm ing/erasing modes. reset clears these bits. eelat ? eeprom latch control bit this read/write bit latches the address and data buses for programming the eeprom array. eelat cannot be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom programming 0 = buses configured for normal read operation eepgm ? eeprom program/erase enable bit this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom array if the eelat bit is set and a write to a valid eeprom location ha s occurred. reset clears the eepgm bit. 1 = eeprom programming/ erasing power switched on 0 = eeprom programming/er asing power switched off note: writing logic 0s to both the eelat and eepgm bits with a single instruction will clear only eepgm. this is to allow time for the removal of high voltage. table 2-4. eeprom program/erase mode select eebpx eeras1 eera0 mode 000byte program 0 0 1 byte erase 0 1 0 block erase 0 1 1 bulk erase 1 x x no erase/program x = don?t care
data sheet mc68hc08as32 ? rev. 4.1 42 freescale semiconductor 2.5.1.7 eeprom non-volatile register and eeprom array configuration register these registers configure the eeprom a rray blocks for programming purposes. eeacr loads its contents from the eenvr register at reset and upon any read of the eenvr register. eera ? eeprom redundant array bit this programmable/erasable/readable bi t in eenvr and read-only bit in eeacr configures the array in redu ndant mode. reset loads eera from eenvr to eeacr. 1 = eeprom array in redundant mode configuration 0 = eeprom array in normal mode configuration eebp3?eebp0 ? eeprom block protection bits these programmable/erasable/readable bi ts in eenvr and read-only bits in eeacr select blocks of eeprom arra y to keep them from being programmed or erased. reset loads eebp[3:0] from eenvr to eeacr. see 2.5.1.3 eeprom block protection . 1 = eeprom array block protected 0 = eeprom array block unprotected address: $fe1f bit 7 6 5 4 3 2 1 bit 0 read: eera r r r eebp3 eebp2 eebp1 eebp0 write:rrrrrrrr reset: eenvr r r r eenvr eenvr eenvr eenvr r= reserved figure 2-4. eeprom array control register (eeacr) address: $fe1c bit 7 6 5 4 3 2 1 bit 0 read: eera r r r eebp3 eebp2 eebp1 eebp0 write: reset:pv r r r pvpvpvpv r = reserved pv = programmed value or 1 in the erased state figure 2-5. eeprom non-volatile register (eenvr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 43 2.5.2 low-power modes the following paragraphs describe the low-power modes. 2.5.2.1 wait mode the wait instruction does not affect t he eeprom. it is possible to program the eeprom while the mcu is in wait mode. however, if the eeprom is inactive, power can be reduced by setting the eeoff bit before executing the wait instruction. 2.5.2.2 stop mode the stop instruction reduces the eeprom power consumption to a minimum. the stop instruction should not be executed while the high voltage is turned on (eepgm = 1). if stop mode is entered while program/erase is in progress, high voltage will be turned off automatically. however, the eepgm bit will remain set. when stop mode is terminated and if eepgm is still se t, the high voltage w ill be turned back on automatically. program/erase time will need to be extended if program/erase is interrupted by entering stop mode. the module requires a recovery time, t eestop , to stabilize after leaving stop mode (see 17.4 5.0-volt dc electrical characteristics ). attempts to access the array during the recovery time will result in unpredictable behavior.
data sheet mc68hc08as32 ? rev. 4.1 44 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 45 data sheet ? mc68hc08as32 section 3. analog-to-digital converter (adc) 3.1 introduction this section describes the 8-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: 15 channels (52-plcc) with multiplexed input linear successive approximation 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 3.3 functional description fifteen adc channels are available for sa mpling external sources at pins ptd6/atd14/tclk ? ptd0/atd8 and ptb7/atd7 ? ptb0/atd0. an analog multiplexer allows the single adc converter to select one of the 15 adc channels as adc voltage input (adcvin). adcvin is converted by the successive approximation register-based counters. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. (see figure 3-2 .)
data sheet mc68hc08as32 ? rev. 4.1 46 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 47 figure 3-2. adc block diagram 3.3.1 adc port i/o pins ptd6/atd14/tclk ? ptd0/atd8 and ptb7/atd7?ptb0/atd0 are general- purpose i/o pins that are shared with the adc channels. the channel select bits (adc status control register, $0038), define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and c an be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. note: do not use adc channel atd14 when us ing the ptd6/atd14/tclk pin as the clock input for the tim. internal data bus read ddrb/ddrb write ddrb/ddrd reset write ptb/ptd read ptb/ptd ptbx/ptdx ddrbx/ddrdx ptbx/ptdx interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x
data sheet mc68hc08as32 ? rev. 4.1 48 freescale semiconductor 3.3.2 voltage conversion when the input voltage to the adc equals v refh (see 17.6 adc characteristics ), the adc converts the signal to $ff (f ull scale). if the input voltage equals v ssa /v refl the adc converts it to $00. input voltages between v refh and v ssa /v refl are a straight-line linear conversion. all other input voltages will result in $ff if greater than v refh and $00 if less than v ssa /v refl . note: input voltage should not exceed the analog supply voltages. 3.3.3 conversion time sixteen adc internal clocks are requir ed to perform one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a write to the adscr. if the ad c internal clock is selected to run at 1 mhz, then one conversion will take 16 s to complete. but since the adc can run almost completely asynchronously to the bus clock, (for example, the adc is configured to derive its internal clock fr om cgmxclk and the bus clock is being derived from the pll within the cgm [cgmout]), this 16- s conversion can take up to 17 s to complete. this wors t-case could occur if the write to the adscr happened directly after the rising edge of the adc internal clock causing the conversion to wait until the next rising edge of the adc internal clock. with a 1-mhz adc internal clock, the maximum sample rate is 59 khz to 62 khz. refer to 17.6 adc characteristics 3.3.4 continuous conversion mode in the continuous conversion mode, the adc continuously converts the selected channel, filling the adc data register with new data after each conversion. data from the previous conversion will be ov erwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit (adc status control register, $0038) is set after each conversion and can be cleared by writing the adc status and control register or reading of the adc data register. 3.3.5 accuracy and precision the conversion process is monotoni c and has no missing codes. see 17.6 adc characteristics for accuracy information. 3.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at 16 to 17 adc clock cycles conversion time = ???????????? adc clock frequency number of bus cycles = c onversion time x bus frequency
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 49 logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the following paragraphs describe the low-power modes. 3.5.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register to logic 1s before executing the wait instruction. 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 3.6 i/o signals the adc module has 15 channels that ar e shared with i/o ports b and d and one channel with an input-only port bit on port d. refer to 17.6 adc characteristics for voltages referenced in the next three subsections. 3.6.1 adc analog power pin (v dda /v ddaref )/adc voltage reference pin (v refh ) the adc analog portion uses v dda /v ddaref as its power pin. connect the v dda /v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda /v ddaref for good results. v refh is the high reference voltage for all analog-to-digital conversions. note: route v dda /v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 3.6.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . v refl is the lower reference supply for the adc. 3.6.3 adc voltage in (adcvin) adcvin is the input voltage signal from one of the 15 adc channels to the adc module.
data sheet mc68hc08as32 ? rev. 4.1 50 freescale semiconductor 3.7 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc input clock register (adiclk) 3.7.1 adc status and control register the following paragraphs describe the function of the adc status and control register. coco ? conversions complete bit in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as a logic 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note: the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $0038 bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 r= reserved figure 3-3. adc status and control register (adscr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 51 adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in table 3-1 . care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (see table 3-1 .) the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note: recovery from the disabled state requires one conversion cycle to stabilize. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptd0/atd8 01001 ptd1/atd9 01010 ptd2/atd10 01011 ptd3/atd11 01100 ptd4/atd12 01101 ptd5/atd13 01110ptd6/atd14/tclk range 01111 ($0f) to 11010 ($1a) unused (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown. 11011 reserved 11100 unused (1) 11101 v refh (2) 2. the voltage levels supplied from internal referenc e nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applications. 11110 v ssa /v refl (2) 11111 adc power off
data sheet mc68hc08as32 ? rev. 4.1 52 freescale semiconductor 3.7.2 adc data register one 8-bit data register is provided. this register is updated each time an adc conversion completes. 3.7.3 adc input clock register this register selects the clock frequency for the adc. adiv2:adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit fi eld which selects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurations. the adc clock s hould be set to approximately 1 mhz. address: $0039 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-4. adc data register (adr) address: $003a bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: rrrr reset: 0 0000000 r= reserved figure 3-5. adc input clock register (adiclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 53 adiclk ? adc input clock register bit adiclk selects either bus clock or cg mxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for t he adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the cl ock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. (see 17.6 adc characteristics .) 1 = internal bus clock 0 = external clock (cgmxclk) note: during the conversion process, changing t he adc clock will result in an incorrect conversion. f xclk or bus frequency 1 mhz = ??????????? adiv[2:0]
data sheet mc68hc08as32 ? rev. 4.1 54 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 55 data sheet ? mc68hc08as32 section 4. byte data link controller-digital (bdlc-d) 4.1 introduction the byte data link controller (bdlc) pr ovides access to an external serial communication multiplex bus, operating according to the society of automotive engineers (sae) j1850 protocol. 4.2 features features include: sae j1850 class b data communication s network interface compatible and iso compatible for low speed (< 125 kbps) serial data communications in automotive applications 10.4 kbps variable pulse width (vpw) bit format digital noise filter collision detection hardware cyclical redundancy check (crc) generation and checking two power-saving modes with automatic wakeup on network activity polling and cpu interrupts available block mode receive and transmit supported supports 4x receive mode, 41.6 kbps digital loopback mode analog loopback mode in-frame response (ifr) types 0, 1, 2, and 3 supported 4.3 functional description figure 4-2 shows the organization of the bdlc module. the cpu interface contains the software addressable regist ers and provides the link between the cpu and the buffers. the buffers provide storage for data received and data to be transmitted onto the j1850 bus. the prot ocol handler is responsible for the encoding and decoding of data bits and special message symbols during transmission and reception. the mux in terface provides the link between the bdlc digital section and the analog physica l interface. the wave shaping, driving, and digitizing of data is performed by the physical interface.
data sheet mc68hc08as32 ? rev. 4.1 56 freescale semiconductor figure 4-1. block diagram highlighting bldc block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 57 use of the bdlc module in messag e networking fully implements the sae standard j1850 class b data communication network interface specification. note: it is recommended that the reader be fa miliar with the sae j1850 document and iso serial communication document prior to proceeding with this section of the mc68hc08as32 specification. figure 4-2. bdlc block diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc addr. register name bit 7 6 5 4 3 2 1 bit 0 $003b bdlc analog and roundtrip delay register (bard) see page 77. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset: 1 1 0 0 0 1 1 1 $003c bdlc control register 1 (bcr1) see page 78. read: imsg clks r1 r0 00 ie wcm write: r r reset: 1 1 1 0 0 0 0 0 $003d bdlc control register 2 (bcr2) see page 80. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset: 1 1 0 0 0 0 0 0 $003e bdlc state vector register (bsvr) see page 85. read: 0 0 i3 i2 i1 i0 0 0 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $003f bdlc data register (bdr) see page 87. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: unaffected by reset r= reserved figure 4-3. bdlc i/o register summary
data sheet mc68hc08as32 ? rev. 4.1 58 freescale semiconductor 4.3.1 bdlc operating modes the bdlc has five main modes of operation which interact with the power supplies, pins, and the remainder of the mcu as shown in figure 4-4 . figure 4-4. bdlc operating modes state diagram 4.3.1.1 power off mode this mode is entered from reset m ode whenever the bdlc supply voltage, v dd , drops below its minimum specified value for the bdlc to guarantee operation. the bdlc will be placed in reset mode by low-voltage reset (lvr) before being powered down. in this mode, the pin input and output specifications are not guaranteed. 4.3.1.2 reset mode this mode is entered from the power off mode whenever the bdlc supply voltage, v dd , rises above its minimum specified value (v dd ?10%) and some mcu reset source is asserted. the internal mcu reset must be asserted while powering up the bdlc or an unknown state will be entered and correct operation cannot be guaranteed. reset mode is also entered from any other mode as soon as one of v dd > v dd (minimum) and power off reset bdlc stop run v dd v dd (minimum) stop instruction or (from any mode) bdlc wait network activity or wait instruction and wcm = 1 wait instruction and wcm = 0 any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wakeup other mcu wakeup cop, illaddr, pu, reset, lvr, por
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 59 the mcu?s possible reset sources (such as lvr, por, cop watchdog, and reset pin, etc.) is asserted. in reset mode, the internal bdlc voltage references are operative; v dd is supplied to the internal circuits which are held in their reset state; and the internal bdlc system clock is running. registers will assume their reset condition. outputs are held in their programmed reset state. therefore, inputs and network activity are ignored. 4.3.1.3 run mode this mode is entered from the reset mode after all mcu reset sources are no longer asserted. run mode is entered from the bdlc wait mode whenever activity is sensed on the j1850 bus. run mode is entered from the bdlc stop mode whenever network activity is sensed, although messages will not be received properly until the clocks have stabilized and the cpu is in run mode also. in this mode, normal network operation takes place. the user should ensure that all bdlc transmissions have ceased before exiting this mode. 4.3.1.4 bdlc wait mode this power-conserving mode is entered aut omatically from run mode whenever the cpu executes a wait instruction and if the wcm bit in the bcr1 register is cleared previously. in this mode, the bdlc internal clocks co ntinue to run. the first passive-to-active transition of the bus generates a cpu interrupt request from the bdlc which wakes up the bdlc and the cpu. in addition, if the bdlc receives a valid eof symbol while operating in wait mode, then the bdlc also will generate a cpu interrupt request which wakes up the bdlc and the cpu. see 4.7.1 wait mode . 4.3.1.5 bdlc stop mode this power-conserving mode is entered aut omatically from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait instruction and the wcm bit in the bcr1 register is set previously. in this mode, the bdlc internal clocks are stopped but the physical interface circuitry is placed in a low-power mode and awaits network activity. if network activity is sensed, then a cpu interrupt request will be generated, restarting the bdlc internal clocks. see 4.7.2 stop mode . 4.3.1.6 digital loopback mode when a bus fault has been detected, the digital loopback mode is used to determine if the fault condition is caused by failure in the node?s internal circuits or
data sheet mc68hc08as32 ? rev. 4.1 60 freescale semiconductor elsewhere in the network, including the node?s analog physical interface. in this mode, the transmit digital output pin (bdtxd) and the receive digital input pin (bdrxd) of the digital interface ar e disconnected from the analog physical interface and tied together to allow the digital portion of the bdlc to transmit and receive its own messages without driving the j1850 bus. 4.3.1.7 analog loopback mode analog loopback is used to determine if a bus fault has been caused by a failure in the node?s off-chip analog transceiver or elsewhere in the network. the bcld analog loopback mode does not modify the di gital transmit or receive functions of the bdlc. it does, however, ensure that once analog loopback mode is exited, the bdlc will wait for an idle bus condition before participation in network communication resumes. if the off-chip analog transceiver has a loopback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the j1850 bus. in this mode, the output to the j1850 bus is typically high impedance. this allows the communication path through the analog transceiver to be tested without interfering with network activity. using the bdlc analog loopback mode in conjunction with the analog transceiver?s loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, th e bcld will not begin communicating before a known condition exists on the j1850 bus. 4.4 bdlc mux interface the mux interface is responsible for bit encoding/decoding and digital noise filtering between the protocol h andler and the physical interface. figure 4-5. bdlc block diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 61 4.4.1 rx digital filter the receiver section of the bdlc includes a digital low-pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 4-6 . figure 4-6. bdlc rx digital filter block diagram 4.4.1.1 operation the clock for the digital filter is provided by the mux interface clock (see f bdlc parameter in table 4-3 ). at each positive edge of the clock signal, the current state of the receiver physical interface (bdrxd) signal is sampled. the bdrxd signal state is used to determine whether the co unter should increment or decrement at the next negative edge of the clock signal. the counter will increment if the input data sample is high but decrement if the input sample is low. therefore, the counter w ill thus progress either up toward 15 if, on average, the bdrxd signal remains high or progress down toward 0 if, on average, the bdrxd signal remains low. when the counter eventually reaches the valu e 15, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can only be decremented from this state. alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 0 and the data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, the counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the signal. 4-bit up/down couter data latch up/down out d q filtered rx data out mux interface input sync dq rx data from physical interface clock (bdrxd)
data sheet mc68hc08as32 ? rev. 4.1 62 freescale semiconductor 4.4.1.2 performance the performance of the digital filter is best described in the time domain rather than the frequency domain. if the signal on the bdrxd signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. this filter delay must be taken into account when performing message arbitration. for example, if the frequency of the mux interface clock (f bdlc ) is 1.0486 mhz, then the period (t bdlc ) is 954 ns and the maximum filter delay in the absence of noise will be 15.259 s. the effect of random noise on the bdrxd signal depends on the characteristics of the noise itself. narrow noise pulses on the bdrxd signal will be ignored completely if they are shorter than the fi lter delay. this provides a degree of low pass filtering. if noise occurs during a symbol transition, the detection of that transition can be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transit ion is truly occurri ng within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, will be detected by the next stage of the bdlc?s receiver as an invalid symbol. noise pulses that are longer than the shor test allowable symbol length will be detected normally as an invalid symbol or as invalid data when the frame?s crc is checked. 4.4.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format shown in figure 4-7 . j1850 states that each message has a maximum length of 101 pwm bit times or 12 vpw bytes, excluding sof, eod, nb, and eof, with each byte transmitted msb first. all vpw symbol lengths in the following descriptions are typical values at a 10.4 kbps bit rate. data e o d optional i f s idle sof priority (data0) message id (data1) data n crc n b ifr eof idle figure 4-7. j1850 bus message format (vpw)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 63 sof ? start-of-frame symbol all messages transmitted onto the j1850 bus must begin with a long-active 200- s period sof symbol. this indicates the start of a new message transmission. the sof symbol is not used in the crc calculation. data ? in-message data bytes the data bytes contained in the message include the message priority/type, message id byte (typically the physica l address of the responder), and any actual data being transmitted to the re ceiving node. the message format used by the bdlc is similar to the 3-by te consolidated header message format outlined by the sae j1850 document. see sae j1850 ? class b data communications network interface for more information about 1- and 3-byte headers. messages transmitted by the bdlc onto the j1850 bus must contain at least one data byte and, therefore, can be as short as one data byte and one crc byte. each data byte in the message is eight bits in length and is transmitted msb to lsb. crc ? cyclical r edundancy check byte this byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message. the bdlc calculates the crc byte and appends it onto any messages transmitted onto the j1850 bus. it also performs crc detection on any messages it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 + x 4 + x 3 + x 2 + 1. the remainder polynomial initially is set to all ones. each byte in the message after the start of frame (sof) symbol is processed serially through the crc generation circuitry. the one?s complement of the remainder then becomes the 8-bit crc byte, which is appended to the message after the data bytes in msb-to-lsb order. when receiving a message, the bdlc us es the same divisor polynomial. all data bytes, excluding the sof and end of data symbols (eod) but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial will equal x 7 + x 6 + x 2 = $c4, regardless of the data contained in the message. if the calculat ed crc does not equal $c4, the bdlc will recognize this as a crc error and set the crc error flag in the bsvr. eod ? end-of-data symbol the eod symbol is a long 200- s passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. no flag is set upon reception of the eod symbol. ifr ? in-frame response bytes the ifr section of the j1850 message format is optional. users desiring further definition of in-frame response should review the sae j1850 ? class b data communications network interface specification.
data sheet mc68hc08as32 ? rev. 4.1 64 freescale semiconductor eof ? end-of-frame symbol this symbol is a long 280- s passive period on the j1850 bus and is longer than an end-of-data (eod) symbol, which signi fies the end of a message. since an eof symbol is longer than a 200- s eod symbol, if no response is transmitted after an eod symbol, it becomes an eof, and the message is assumed to be completed. the eof flag is set upon receiving the eof symbol. ifs ? inter-frame separation symbol the ifs symbol is a 20- s passive period on the j1850 bus which allows proper synchronization between nodes during c ontinuous message transmission. the ifs symbol is transmitted by a node after the completion of the end-of-frame (eof) period and, therefore, is seen as a 300- s passive period. when the last byte of a message has been transmitted onto the j1850 bus and the eof symbol time has expired, all nodes then must wait for the ifs symbol time to expire before transmitting a start-of-frame (sof) symbol, marking the beginning of another message. however, if the bdlc is waiting for the ifs period to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it will synchronize internally to that edge. if a write to the bdr register (for instance, to initiate transmission) occurred on or before 104 t bdlc from the received rising edge, then the bdlc will transmit and arbitrate for the bus. if a cpu write to the bdr register occurred after 104 t bdlc from the detection of the rising edge, then the bdlc will not transmit, but will wait for the next ifs period to expire before attempting to transmit the byte. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, ca using different nodes to observe the completion of the ifs period at different times. to allow for individual clock tolerances, receivers must synchronize to any sof occurring during an ifs period. break ? break the bdlc cannot transmit a break symbol. if the bdlc is transmitting at the time a break is detected, it treats the break as if a transmission error had o ccurred and halts transmission. if the bdlc detects a break symbol whil e receiving a message, it treats the break as a reception error and sets the invalid symbol flag in the bsvr, also ignoring the frame it was receiving. if while receiving a message in 4x mode, the bdlc detects a break symbol, it tr eats the break as a reception error, sets the invalid symbol flag, and exits 4x mode (for example, the rx4xe bit in bcr2 is cleared automatically). if bu s control is required after the break symbol is received and the ifs time has elapsed, the programmer must resend the transmission byte using highest priority. note: the j1850 protocol break symbol is not re lated to the hc08 break module (see section 16. development support .)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 65 idle ? idle bus an idle condition exists on the bus during any passive period after expiration of the ifs period (for instance, 300 s). any node sensing an idle bus condition can begin transmission immediately. 4.4.3 j1850 vpw symbols huntsinger?s variable pulse width modulation (vpw) is an encoding technique in which each bit is defined by the time bet ween successive transitions and by the level of the bus between transitions (for in stance, active or passive). active and passive bits are used alternately. this encoding technique is used to reduce the number of bus transitions for a given bit rate. each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one of two lengths, either 64 s or 128 s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the start-of-frame (sof), end-of-data (eod), end-of-frame (eof), and inter-frame separation (ifs) symbols always will be encoded at an assigned level and length. see figure 4-8 . figure 4-8. j1850 vpw symbols with nominal symbol times 128 s active passive 64 s or (a) logic 0 128 s active passive 64 s or ( b) logic 1 200 s active passive ( d) start of frame active passive (f) end of frame 240 s (c) break 200 s ( e) end of data 280 s (g) inter-frame 20 s 300 s idle > 300 s (h) idle separation
data sheet mc68hc08as32 ? rev. 4.1 66 freescale semiconductor each message will begin with an sof symbol an active symbol and, therefore, each data byte (including the crc byte) wi ll begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. all vpw bit lengths stated in the followi ng descriptions are typical values at a 10.4 kbps bit rate. logic 0 a logic 0 is defined as either: ? an active-to-passive transition followed by a passive period 64 s in length, or ? a passive-to-active transition followed by an active period 128 s in length see figure 4-8 (a) . logic 1 a logic 1 is defined as either: ? an active-to-passive transition followed by a passive period 128 s in length, or ? a passive-to-active transition followed by an active period 64 s in length see figure 4-8 (b) . normalization bit (nb) the nb symbol has the same property as a logic 1 or a logic 0. it is only used in ifr message responses. break signal (break) the break signal is defined as a passive-to-active transition followed by an active period of at least 240 s (see figure 4-8 (c) ). start-of-frame symbol (sof) the sof symbol is defined as passive-to- active transition followed by an active period 200 s in length (see figure 4-8 (d) ). this allows t he data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. end-of-data symbol (eod) the eod symbol is defined as an active-to-passive transition followed by a passive period 200 s in length (see figure 4-8 (e) ). end-of-frame symbol (eof) the eof symbol is defined as an acti ve-to-passive transition followed by a passive period 280 s in length (see figure 4-8 (f) ). if no ifr byte is transmitted after an eod symbol is transmitted, after another 80 s the eod becomes an eof, indicating completion of the message.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 67 inter-frame separation symbol (ifs) the ifs symbol is defined as a passive period 300 s in length. the 20- s ifs symbol contains no transition, sinc e when used it always appends to an eof symbol (see figure 4-8 (g) ). idle an idle is defined as a passive period greater than 300 s in length. 4.4.4 j1850 vpw valid/invalid bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in o scillator frequencies. in many cases the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol. since the minimum resolution of the bdlc for determining what symbol is being received is equal to a single period of the mux interface clock (t bdlc ), an apparent separation in these maximum time/minimum time concurrences equal to one cycle of t bdlc occurs. this one clock resolution allows the bdlc to differentiate properly between the different bits and symbols. this is do ne without reducing the valid window for receiving bits and symbols from trans mitters onto the j1850 bus which have varying oscillator frequencies. figure 4-9. j1850 vpw received passive symbol times a bc b a (1) invalid passive bit (2) valid passive logic 0 (3) valid passive logic 1 64 s 128 s cd (4) valid eod symbol 200 s active passive active passive active passive active passive
data sheet mc68hc08as32 ? rev. 4.1 68 freescale semiconductor in huntsinger?s? variable pulse widt h (vpw) modulation bit encoding, the tolerances for both the passive and acti ve data bits received and the symbols received are defined with no gaps between definitions. for example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1, and the maximum length of an active logic 0 is equal to the minimum length of a valid sof symbol. invalid passive bit see figure 4-9 (1) . if the passive-to-active received transition beginning the next data bit or symbol occurs bet ween the active-to-passive transition beginning the current data bit (or symbol) and a , the current bit would be invalid. valid passive logic 0 see figure 4-9 (2) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 0. valid passive logic 1 see figure 4-9 (3) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 1. valid eod symbol see figure 4-9 (4) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid end-of-data symbol (eod). figure 4-10. j1850 vpw received passive eof and ifs symbol times valid eof and ifs symbol in figure 4-10 (1) , if the passive-to-active rece ived transition beginning the sof symbol of the next message occurs between a and b , the current symbol will be considered a valid end-of-frame (eof) symbol. cd (2) valid eof+ 280 s 300 s a b ( 1) valid eof symbol active passive active passive ifs symbol
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 69 see figure 4-10 (2) . if the passive-to-active received transition beginning the sof symbol of the next message occurs between c and d , the current symbol will be considered a valid eof symbol followed by a valid inter-frame separation symbol (ifs). all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, due to variations in clock frequencies and bus loading, some nodes may recognize a valid ifs symbol before others and immediately begin transmitting. th erefore, any time a node waiting to transmit detects a passive-to-active transition once a valid eof has been detected, it should immediately begin tr ansmission, initiating the arbitration process. idle bus in figure 4-10 (2) , if the passive-to-active received transition beginning the start-of-frame (sof) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. figure 4-11. j1850 vpw received active symbol times invalid active bit in figure 4-11 (1) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between t he passive-to-active transition beginning the current data bit (or symbol) and a , the current bit would be invalid. a bc b a (1) invalid active bit (2) valid active logic 1 (3) valid active logic 0 64 s 128 s cd (4) valid sof symbol 200 s active passive active passive active passive active passive
data sheet mc68hc08as32 ? rev. 4.1 70 freescale semiconductor valid active logic 1 in figure 4-11 (2) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 1. valid active logic 0 in figure 4-11 (3) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 0. valid sof symbol in figure 4-11 (4) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid sof symbol. valid break symbol in figure 4-12 , if the next active-to-passive received transition does not occur until after e , the current symbol will be considered a valid break symbol. a break symbol should be followed by a st art-of-frame (sof) symbol beginning the next message to be transmitted onto the j1850 bus. see 4.4.2 j1850 frame format for bdlc response to break symbols. figure 4-12. j1850 vpw received break symbol times 4.4.5 message arbitration message arbitration on the j1850 bus is accomplished in a non-destructive manner, allowing the message with the highes t priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the bdlc wants to transmit onto the j1850 bus, but detects that another message is in progress, it waits until the bus is idle. however, if multiple nodes begin to transmit in the same synchroni zation window, message arbitration will occur beginning with the first bit after t he sof symbol and will continue with each bit thereafter. (2) valid break symbol 240 s e active passive
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 71 figure 4-13. j1850 vpw bitwise arbitrations the variable pulse width modulation (vpw) symbols and j1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive type) that is simultaneously transmitted. hence, logic 0s are said to be dominant and logic 1s are said to be recessive. whenever a node detects a dominant bit on bdrxd when it transmitted a recessive bit, the node loses arbitration and immediately stops transmitting. this is known as bitwise arbitration. since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitration. for instance, a message with priority 000 will win arbitration over a message with priority 011. this method of arbitration will work no matter how many bits of priority encoding are contained in the message. during arbitration, or even throughout the transmitting message, when an opposite bit is detected, transmission is stopped im mediately unless it occurs on the 8th bit of a byte. in this case, the bdlc automatically will append up to two extra logic 1 bits and then stop transmitting. these two ex tra bits will be arbitrated normally and thus will not interfere with another message. the second logic 1 bit will not be sent if the first loses arbitration. if the bdlc has lost arbitration to another valid message, then the two extra logic 1s will not corrupt the current message. however, if the bdlc has lost arbitration due to noise on the bus, then the two extra logic 1s will ensure that the cu rrent message will be detected and ignored as a noise-corrupted message. transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 0 transmitter a detects an active state on the bus and stops transmitting transmitter b wins passive active passive active passive active 0 0 1 1 1 data bit 2 1 1 1 data bit 3 0 0 0 0 1 arbitration and continues transmitting
data sheet mc68hc08as32 ? rev. 4.1 72 freescale semiconductor 4.5 bdlc prot ocol handler the protocol handler is responsible for framing, arbitration, crc generation/checking, and error detection. the protocol handler conforms to sae j1850 ? class b data communi cations network interface . note: freescale assumes that the reader is fa miliar with the j1850 specification before this protocol handler description is read. figure 4-14. bdlc block diagram 4.5.1 protocol architecture the protocol handler contains the state machine, rx shadow register, tx shadow register, rx shift register, tx shift regi ster, and loopback multiplexer as shown in figure 4-15 . 4.5.2 rx and tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx shadow register. the tx shift register takes data, in parallel form, from the tx shadow register and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 73 figure 4-15. bdlc protocol handler outline 4.5.3 rx and tx shadow registers immediately after the rx shift register has completed shifting in a byte of data, this data is transferred to the rx shadow register and rdrf or rxifr is set (see 4.6.4 bdlc state vector register ) and an interrupt is generated if the interrupt enable bit (ie) in bcr1 is set. after the transfer takes place, this new data byte in the rx shadow register is available to the cpu inte rface, and the rx shift register is ready to shift in the next byte of data. data in the rx shadow register must be retrieved by the cpu before it is overwritten by new data from the rx shift register. once the tx shift register has completed its shifting operation for the current byte, the data byte in the tx shadow register is loaded into the tx shift register. after this transfer takes place, the tx shadow regist er is ready to accept new data from the cpu when tdre flag in bsvr is set. 4.5.4 digital loopback multiplexer the digital loopback multiplexer connec ts rxd to either bdtxd or bdrxd, depending on the state of the dloop bit in the bcr2 register (see 4.6.3 bdlc control register 2 ). rx shift register to cpu interface and rx/tx buffers state machine to physical interface rx data tx data control 8 tx shift register bdtxd rxd control 8 rx shadow register tx shadow register loopback bdrxd bdtxd multiplexer dloop from bcr2 aloop loopback control
data sheet mc68hc08as32 ? rev. 4.1 74 freescale semiconductor 4.5.5 state machine all of the functions associated with performing the protocol are executed or controlled by the state machine. the state machine is responsible for framing, collision detection, arbitration, crc gener ation/checking, and error detection. the following sections describe the bdlc?s actions in a variety of situations. 4.5.5.1 4x mode the bdlc can exist on the same j1850 bus as modules which use a special 4x (41.6 kbps) mode of j1850 variable pulse width modulation (vpw) operation. the bdlc cannot transmit in 4x mode, but can receive messages in 4x mode, if the rx4x bit is set in bcr2 register. if the rx4x bit is not set in the bcr2 register, any 4x message on the j1850 bus is treated as noise by the bdlc and is ignored. 4.5.5.2 receiving a message in block mode although not a part of the sae j1850 protocol, the bdlc does allow for a special block mode of operation of the receiver. as far as the bdlc is concerned, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all of the other features of the frame remain the same, including the sof, crc, and eod symbols. another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. this is usually accomplished by sending a special predefined message. 4.5.5.3 transmitting a message in block mode a block mode message is transmitted inher ently by simply loading the bytes one by one into the bdr register until the message is complete. the programmer should wait until the tdre flag (see 4.6.4 bdlc state vector register ) is set prior to writing a new byte of data into the bdr register. the bdlc does not contain any predefined maximum j1850 message length requirement. 4.5.5.4 j1850 bus errors the bdlc detects several types of transmit and receive errors which can occur during the transmission of a message onto the j1850 bus. transmission error if the message transmitted by the bdlc co ntains invalid bits or framing symbols on non-byte boundaries, this consti tutes a transmission error. when a transmission error is detected, the bd lc immediately will cease transmitting. the error condition ($1c) is reflected in the bsvr register (see table 4-5 ). if the interrupt enable bit (ie in bcr1) is set, a cpu interrupt request from the bdlc is generated.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 75 crc error a cyclical redundancy check (crc) error is detect ed when the data bytes and crc byte of a received message are pr ocessed and the crc calculation result is not equal to $c4. the crc code will det ect any single and 2-bit errors, as well as all 8-bit burst errors and almost a ll other types of errors. the crc error flag ($18 in bsvr) is set when a crc error is detected. (see 4.6.4 bdlc state vector register .) symbol error a symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the j1850 bus. however, if the bdlc is transmitting when this happens, it will be treated as a loss of arbitration ($14 in bsvr) rather than a transmitter error. the ($1c) symbol invalid or the out-of-range flag is set when a symbol error is detected. therefore, ($1c) symbol invalid flag is stacked behind the ($14) loa flag during a transmission error process. (see 4.6.4 bdlc state vector register .) framing error a framing error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. a framing erro r also is detected if the bdlc is transmitting the eod and instead receives an active symbol. the ($1c) symbol invalid or the out-of-range flag is set when a framing error is detected. (see 4.6.4 bdlc state vector register .) bus fault if a bus fault occurs, the response of t he bdlc will depend upon the type of bus fault. if the bus is shorted to battery, the bdlc will wait for the bus to fall to a passive state before it will attempt to transmit a message. as long as the short remains, the bdlc will never attempt to transmit a message onto the j1850 bus. if the bus is shorted to ground, the bdlc will see an idle bus, begin to transmit the message, and then detect a transmi ssion error ($1c in bsvr), since the short to ground would not allow the bus to be driven to the active (dominant) sof state. the bdlc will abort that transmission and wait for the next cpu command to transmit. in any case, if the bus fault is temporar y, as soon as the fault is cleared, the bdlc will resume normal operation. if the bus fault is permanent, it may result in permanent loss of communication on the j1850 bus. (see 4.6.4 bdlc state vector register .) break ? break if a break symbol is received while the bd lc is transmitting or receiving, an invalid symbol ($1c in bsvr) interrupt will be generated. reading the bsvr register (see 4.6.4 bdlc state vector register ) will clear this interrupt condition. the bdlc will wait for the bus to idle, then wait for a start-of-frame (sof) symbol. the bdlc cannot transmit a break symbol. it can only receive a break symbol from the j1850 bus.
data sheet mc68hc08as32 ? rev. 4.1 76 freescale semiconductor 4.5.5.5 summary 4.6 bdlc cpu interface the cpu interface provides the interface between the cpu and the bdlc and consists of five user registers. bdlc analog and roundtrip delay register (bard) bdlc control register 1 (bcr1) bdlc control register 2 (bcr2) bdlc state vector register (bsvr) bdlc data register (bdr) figure 4-16. bdlc block diagram table 4-1. bdlc j1850 bus error summary error condition bdlc function transmission error for invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. bdlc stops transmission. cyclical redundancy check (crc) error crc error interrupt will be generated. the bdlc will wait for sof. invalid symbol: bdlc receives invalid bits (noise) the bdlc will abort transmission immediately. invalid symbol interrupt will be generated. framing error invalid symbol interrupt will be generated. the bdlc will wait for start-of-frame (sof). bus short to v dd the bdlc will not transmit until the bus is idle. bus short to gnd thermal overload will shut down physical interface. fault condition is reflected in bsvr as an invalid symbol. bdlc receives break symbol. the bdlc will wait for the next valid sof. invalid symbol interrupt will be generated. cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 77 4.6.1 bdlc analog and roundtrip delay register this register programs the bdlc to compensate for various delays of different external transceivers. th e default delay value is16 s. timing adjustments from 9 s to 24 s in steps of 1 s are available. the bard register can be written only once after each reset, after which they become read-only bits. the register may be read at any time. ate ? analog transceiver enable bit the analog transceiver enable (ate) bit is used to select either the on-board or an off-chip analog transceiver. 1 = select on-board analog transceiver 0 = select off-chip analog transceiver note: this device does not contain an on-board transceiver. this bit should be programmed to a logic 0 for proper operation. rxpol ? receive pin polarity bit the receive pin polarity (rxpol) bit is us ed to select the polarity of an incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding it back to the digital receive pin. 1 = select normal/true polarity; true non-inverted signal from the j1850 bus; for example, the external transceiver does not invert the receive signal 0 = select inverted polarity, where an external transceiver inverts the receive signal from the j1850 bus b03?b00 ? bard offset bits table 4-2 shows the expected transceiver del ay with respect to bard offset values. address: $003b bit 7654321bit 0 read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset:11000111 r= reserved figure 4-17. bdlc analog and roundtrip delay register (bard) table 4-2. bdlc transceiver delay bard offset bits b0[3:0] corresponding expected transceiver?s delays ( s) 0000 9 0001 10 0010 11 0011 12 0100 13
data sheet mc68hc08as32 ? rev. 4.1 78 freescale semiconductor 4.6.2 bdlc control register 1 this register is used to configure and control the bdlc. imsg ? ignore message bit this bit is used to disable the receiver until a new start-of-frame (sof) is detected. 1 = disable receiver. when set, all bdlc interrupt requests will be masked and the status bits will be held in thei r reset state. if this bit is set while the bdlc is receiving a message, th e rest of the incoming message will be ignored. 0 = enable receiver. this bit is cleared automatically by the reception of an sof symbol or a break symbol. it wi ll then generate interrupt requests and will allow changes of the status register to occur. however, these interrupts may still be masked by the interrupt enable (ie) bit. 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 table 4-2. bdlc transceiver delay (continued) bard offset bits b0[3:0] corresponding expected transceiver?s delays ( s) address: $003c bit 7654321bit 0 read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 r= reserved figure 4-18. bdlc control register 1 (bcr1)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 79 clks ? clock bit the nominal bdlc operating frequency (f bdlc ) must always be 1.048576 mhz or 1 mhz for j1850 bus communications to take place. the clks register bit allows the user to select the frequency (1.048576 mhz or 1 mhz) used to adjust symbol timing automatically. 1 = binary frequency (1.048576 mhz) selected for f bdlc 0 = integer frequency (1 mhz) selected for f bdlc r1 and r0 ? rate select bits these bits determine the amount by which the frequency of the mcu cgmxclk signal is divided to form the mux interface clock (f bdlc ) which defines the basic timing resolution of the mux interface. they may be written only once after reset, after which they become read-only bits. the nominal frequency of f bdlc must always be 1.048576 mhz or 1.0 mhz for j1850 bus communications to take place. hence, the value programmed into these bits is dependent on the chosen mcu system clock frequency per table 4-3 . ie? interrupt enable bit this bit determines whether the bdlc will generate cpu interrupt requests in run mode. it does not affect cpu interrupt requests when exiting the bdlc stop or bdlc wait modes. interrupt requests will be maintained until all of the interrupt request sources are cleared by performing the specified actions upon the bdlc?s registers. interrupts that were pending at the time that this bit is cleared may be lost. 1 = enable interrupt requests from bdlc 0 = disable interrupt requests from bdlc if the programmer does not wish to use the interrupt capability of the bdlc, the bdlc state vector register (bsvr) can be polled periodically by the programmer to determine bdlc states. see 4.6.4 bdlc state vector register for a description of the bsvr. table 4-3. bdlc rate selection f xclk frequency r1 r0 division f bdlc 1.049 mhz 0 0 1 1.049 mhz 2.097 mhz 0 1 2 1.049 mhz 4.194 mhz 1 0 4 1.049 mhz 8.389 mhz 1 1 8 1.049 mhz 1.000 mhz 0 0 1 1.00 mhz 2.000 mhz 0 1 2 1.00 mhz 4.000 mhz 1 0 4 1.00 mhz 8.000 mhz 1 1 8 1.00 mhz
data sheet mc68hc08as32 ? rev. 4.1 80 freescale semiconductor wcm ? wait clock mode bit this bit determines the operation of the bdlc during cpu wait mode. see 4.7.2 stop mode and 4.7.1 wait mode for more details on its use. 1 = stop bdlc internal cl ocks during cpu wait mode 0 = run bdlc internal clocks during cpu wait mode 4.6.3 bdlc control register 2 this register controls transmitter operations of the bdlc. it is recommended that bset and bclr instructions be used to m anipulate data in this register to ensure that the register?s content does not change inadvertently. aloop ? analog loopback mode bit this bit determines whether the j1850 bus will be driven by the analog physical interface?s final drive stage. the programme r can use this bit to reset the bdlc state machine to a known state after the off-chip analog transceiver is placed in loopback mode. when the user clears aloop, to indicate that the off-chip analog transceiver is no longer in loopback mode, the bdlc waits for an eof symbol before attempting to transmit. 1 = input to the analog physical interface?s final drive stage is looped back to the bdlc receiver. the j1850 bus is not driven. 0 = the j1850 bus will be driven by the bdlc. after the bit is cleared, the bdlc requires the bus to be idle fo r a minimum of end-of-frame symbol time (t trv4 ) before message reception or a minimum of inter-frame symbol time (t trv6 ) before message transmission. (see 17.15 bdlc receiver vpw symbol timings .) dloop ? digital loopback mode bit this bit determines the source to which the digital receive input (bdrxd) is connected and can be used to isol ate bus fault conditions (see figure 4-15 ). if a fault condition has been detected on t he bus, this control bit allows the programmer to connect the digital transmit output to the digital receive input. in this configuration, data sent from the tr ansmit buffer will be reflected back into the receive buffer. if no faults exist in the bdlc, the fault is in the physical interface block or elsewhere on the j1850 bus. 1 = when set, bdrxd is connected to bdtxd. the bdlc is now in digital loopback mode. 0 = when cleared, bdtxd is not connected to bdrxd. the bdlc is taken out of digital loopback mode and can now drive the j1850 bus normally. address: $003d bit 7654321bit 0 read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 figure 4-19. bdlc control register 2 (bcr2)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 81 rx4xe ? receive 4x enable bit this bit determines if the bdlc operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. this feature is useful for fast download of data into a j1850 node for diagnostic or factory programming of the node. 1 = when set, the bdlc is put in 4x receive-only operation. 0 = when cleared, the bdlc transmits and receives at 10.4 kbps. nbfs ? normalization bit format select bit this bit controls the format of the normalization bit (nb). (see figure 4-20 .) sae j1850 strongly encourages using an active long (logic 0) for in-frame responses containing cyclical redundancy check (crc ) and an active short (logic 1) for in-frame responses without crc. 1 = nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) does not end with a crc byte. 0 = nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) does not end with a crc byte. teod ? transmit end of data bit this bit is set by the programmer to in dicate the end of a message is being sent by the bdlc. it will append an 8-bit crc after completing transmission of the current byte. this bit also is used to end an in-frame response (ifr). if the transmit shadow register is full w hen teod is set, the crc byte will be transmitted after the current byte in the tx shift register and the byte in the tx shadow register have been transmitted. (see 4.5.3 rx and tx shadow registers for a description of the transmit shadow register.) once teod is set, the transmit data register empty flag (tdre) in the bdlc state vector register (bsvr) is cleared to allow lower priority interrupts to occur. (see 4.6.4 bdlc state vector register .) 1 = transmit end-of-data (eod) symbol 0 = the teod bit will be cleared automatically at the rising edge of the first crc bit that is sent or if an error is detected. when teod is used to end an ifr transmission, teod is clear ed when the bdlc receives back a valid eod symbol or an error condition occurs. tsifr, tmifr1, and tmifr0 ? transmit in-frame response control bits these three bits control the type of in-frame response being sent. the programmer should not set more than one of these control bits to a 1 at any given time. however, if more than one of these three control bits are set to 1, the priority encoding logic will force th ese register bits to a known value as shown in table 4-4 . for example, if 011 is wr itten to tsifr, tmifr1, and tmifr0, then internally they will be encoded as 010. however, when these bits are read back, they will read 011.
data sheet mc68hc08as32 ? rev. 4.1 82 freescale semiconductor the bdlc supports the in-frame response (ifr) feature of j1850 by setting these bits correctly. the four types of j1850 ifr are shown below. the purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal id or physical address in a concatenated manner after they have seen the eod symbol. if transmission arbitration is lost by a node while sending its response, it continues to transmit its id/address until observing its unique byte in the response stream. for vpw modulation, because the first bit of the if r is always passive, a normalization bit (active) must be generated by the responder and sent prior to its id/address byte. when there are multiple responders on the j1850 bus, only one normalization bit is sent which assists all other transmitting nodes to sync up their response. figure 4-20. types of in-frame response (ifr) table 4-4. bdlc transmit in-frame response control bit priority encoding write/read tsifr write/read tmifr1 write/read tmifr0 actual tsifr actual tmifr1 actual tmifr0 000000 1xx100 01x010 001001 sof header data field crc eod type 0 ? no ifr header data field crc eod type 3 ? multiple bytes transmitted from a single responder header data field crc eod type 1 ? single byte transmitted from a single responder header data field crc eod type 2 ? single byte transmitted from multiple responders id1 id n ifr data field crc nb nb nb id sof sof sof eof eod eof eod eof eod eof (optional) nb = normalization bit id = identifier (usually the phy sical address of the responder(s))
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 83 tsifr ? transmit single byte ifr with no crc (type 1 or 2) bit the tsifr bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr, $003f) as a single byte ifr with no crc. typically, the byte transmitted is a unique identifier or address of the transmitting (responding) node. see figure 4-20 . 1 = if this bit is set prior to a va lid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transmit the appropriate normalization bit followed by the byte in the bdr. 0 = the tsifr bit will be cleared automatically, once the bdlc has successfully transmitted the byte in the bdr onto the bus, or teod is set, or an error is detected on the bus. if the programmer attempts to set th e tsifr bit immediately after the eod symbol has been received from the bus, the tsifr bit will remain in the reset state and no attempt will be made to transmit the ifr byte. if a loss of arbitration occurs when the bdlc attempts to transmit and after the ifr byte winning arbitration completes transmission, the bdlc will again attempt to transmit the bdr (with no normalization bit). the bdlc will continue transmission attempts until an error is detected on the bus, or teod is set, or the bdlc transmission is successful. if loss or arbitration occurs in the last two bits of the ifr byte, two additional 1bits will not be sent out because the bdlc wi ll attempt to retransmit the byte in the transmit shift register after the irf byte winning arbitration completes transmission. tmifr1 ? transmit multiple by te ifr with crc (type 3) bit the tmifr1 bit requests the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a mu ltiple byte ifr with crc or as a single byte ifr with crc. response ifr byte s are still subject to j1850 message length maximums (see 4.4.2 j1850 frame format and figure 4-20 ). if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transmit the appropriate normalization bi t followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr register. after teod has been set and the last ifr byte has been transmitted, the crc byte is transmitted. 0 = the tmifr1 bit will be cleared automatically ? once the bdlc has successfully transmitted the crc byte and eod symbol ? by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr1 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 4.6.4 bdlc state vector register ) will occur similar to the ma in message transmit sequence.
data sheet mc68hc08as32 ? rev. 4.1 84 freescale semiconductor the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bdlc control register 2 (bcr2). this will instruct the bdlc to transmit a crc byte once the byte in the bdr is transmitted and then transmit an eod sy mbol, indicating the end of the ifr portion of the message frame. however, if the programmer wishes to transmit a single byte followed by a crc byte, the programmer should load the byte into the bdr before the eod symbol has been received, and then set the tmifr1 bit. once the tdre interrupt occurs, the programmer should then set t he teod bit in the bcr2. this will result in the byte in the bdr being t he only byte transmitted before the ifr crc byte, and no tdre interrupt will be generated. if the programmer attempts to set the tmifr1 bit immediately after the eod symbol has been received from the bus, the tmifr1 bit will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting any byte of a multiple byte ifr, the bdlc will go to the loss of arbitration state, set the appropriate flag, and cease transmission. if the bdlc loses arbitration during the ifr, the tmifr1 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitration occurs in the last two bits of th e ifr byte, two additional 1 bits will be sent out. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. tmifr0 ? transmit multiple byte ifr without crc (type 3) bit the tmifr0 bit is used to request the bd lc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr without crc. response ifr bytes are still subjec t to j1850 message length maximums (see 4.4.2 j1850 frame format and figure 4-20 ). 1 = if this bit is set prior to a va lid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transmit the appropriate normalizatio n bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr register. after teod has been set, the last ifr byte to be transmitted will be the last byte which was written into the bdr register. 0 = the tmifr0 bit will be cleared automatically; once the bdlc has successfully transmitted the eod symbol; by the detection of an error on the multiplex bus; or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr0 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 4.6.4 bdlc state vector register ) will occur similar to the ma in message transmit sequence.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 85 the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bcr2. this will instruct the bdlc to transmit an eod symbol once the byte in the bdr is transmitted, indicating the end of the ifr portion of the message frame. the bdlc will not append a crc when the tmifr0 is set. if the programmer attempts to set the tmifr0 bit after the eod symbol has been received from the bus, the tmifr0 bi t will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting, the tmifr0 bit will be cleared and no attempt will be made to re transmit the byte in the bdr. if loss of arbitration occurs in the last two bi ts of the ifr byte, two additional 1 bits (active short bits) will be sent out. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. 4.6.4 bdlc state vector register this register is provided to substantially decrease the cpu overhead associated with servicing interrupts while under operation of a multiplex protocol. it provides an index offset that is directly related to the bdlc?s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the user to maintain a duplicate state machine in software. i0, i1, i2, and i3 ? interrupt source bits these bits indicate the source of the in terrupt request that currently is pending. the encoding of these bits are listed in table 4-5 . bits i0, i1, i2, and i3 are cleared by a read of the bsvr except when the bdlc data register needs servicing (rdrf, rx ifr, or tdre conditions). rxifr and rdrf can be cleared only by a read of the bsvr followed by a read of the bdlc data register (bdr). tdre can eit her be cleared by a read of the bsvr followed by a write to the bdlc bdr or by setting the teod bit in bcr2. address: $003e bit 7654321bit 0 read:0 0 i3i2i1i0 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 4-21. bdlc state vector register (bsvr)
data sheet mc68hc08as32 ? rev. 4.1 86 freescale semiconductor upon receiving a bdlc inte rrupt, the user can read the value within the bsvr, transferring it to the cpu?s index register. the value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine. for example: note: the nops are used only to align the jmps onto 4-byte boundaries so that the value in the bsvr can be used intact. each of t he service routines must end with an rti instruction to guarantee correct continued operation of the device. note also that the first entry can be omitted since it corresponds to no interrupt occurring. the service routines should clear all of the sources that are causing the pending interrupts. note that the clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits i0, i1, and i2 of the bsvr will then reflect the source of the remaining interrupt request. if fewer states are used or if a different software approach is taken, the jump table can be made smaller or omitted altogether. table 4-5. bdlc interrupt sources bsvr i3 i2 i1 i0 interrupt source priority $00 0000 no interrupts pending 0 (lowest) $04 0001 received eof 1 $08 0010 received ifr byte (rxifr) 2 $0c 0011 bdlc rx data register full ( rdrf) 3 $10 0100 bdlc tx data register empty (tdre) 4 $14 0101 loss of arbitration 5 $18 0110 cyclical redundancy check ( crc) error 6 $1c 0111 symbol invalid or out of range 7 $20 1000 wakeup 8 (highest) service ldx bsvr fetch state vector number jmp jmptab,x enter service routine, * (must end in rti) * jmptab jmp serve0 service condition #0 nop jmp serve1 service condition #1 nop jmp serve2 service condition #2 nop * jmp serve8 service condition #8 end
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 87 4.6.5 bdlc data register this register is used to pass the data to be transmitted to the j1850 bus from the cpu to the bdlc. it is also used to pa ss data received from the j1850 bus to the cpu. each data byte (after the first one) should be written only after a tx data register empty (tdre) state is indicated in the bsvr. data read from this register will be the la st data byte received from the j1850 bus. this received data should only be read after an rx data register full (rdrf) interrupt has occurred. (see 4.6.4 bdlc state vector register .) the bdr is double buffered via a transmi t shadow register and a receive shadow register. after the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. once the transmit sh ift register has shifted the first bit out, the tdre flag is set, and the shadow register is ready to accept the next data byte. the receive shadow register works similarly. once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. the rdrf flag is set to indicate that a new byte of data has been received. the programmer has one bdlc byte recept ion time to read the shadow register and clear the rdrf flag before the shadow register is overwritten by the newly received byte. to abort an in-progress transmission, t he programmer should stop loading data into the bdr. this will cause a transmitter underrun error and the bdlc automatically will disable the transm itter on the next non-byte boundary. this means that the earliest a tr ansmission can be halted is after at least one byte plus two extra logic 1s have been transmitted. the receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. address: $003f bit 7654321bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: reset: unaffected by reset figure 4-22. bdlc data register (bdr)
data sheet mc68hc08as32 ? rev. 4.1 88 freescale semiconductor 4.7 low-power modes the following information concerns wait mode and stop mode. 4.7.1 wait mode this power-conserving mode is entered aut omatically from run mode whenever the cpu executes a wait instruction and the wcm bit in bdlc control register 1 (bcr1) is previously clear. in bdlc wait mode, the bdlc cannot drive any data. a subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the bdlc to wake up and generate a cpu interrupt request if the interrupt enable (ie) bit in the bdlc control register 1 (bcr1) is previously set. (see 4.6.2 bdlc control register 1 for a better understanding of ie.) this results in less of a power saving, but the bdlc is guaranteed to receive correctly the message which woke it up, since the bdlc internal operating clocks are kept running. note: ensuring that all transmissions are complete or aborted before putting the bdlc into wait mode is important. 4.7.2 stop mode this power-conserving mode is entered aut omatically from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait instruction and the wcm bit in the bdlc control register 1 (bcr1) is previously set. this is the lowest power mode that the bdlc can enter. a subsequent passive-to-active transition on the j1850 bus will cause the bdlc to wake up and generate a non-maskable cpu interrupt request. when a stop instruction is used to put the bdlc in stop mode, the bdlc is not guaranteed to correctly receive the message which woke it up, since it may take some time for the bdlc internal operating clocks to restart and stabilize. if a wait instruction is used to put the bdlc in stop mode, the bdlc is guaranteed to correctly receive the byte which woke it up, if and only if an end-of-frame (eof) has been detected prior to issuing the wait instruction by the cpu. otherwise, the bdlc will not correctly receive the byte that woke it up. if this mode is entered while the bdlc is receiving a message, the first subsequent received edge will cause the bdlc to wake up immediately, generate a cpu interrupt request, and wait for the bdlc in ternal operating clocks to restart and stabilize before normal communications can resume. therefore, the bdlc is not guaranteed to receive that message correctly. note: it is important to ensure all transmissions are complete or aborted prior to putting the bdlc into stop mode.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 89 data sheet ? mc68hc08as32 section 5. clock generator module (cgm) 5.1 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock si gnal, cgmout, from which the system integration module (sim) derives the sy stem clocks. cgmout is based on either the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with 1-mhz to 16-mhz crystals or ceramic resonato rs. the pll can generate an 8-mhz bus frequency without using a 32-mhz crystal. 5.2 features features of the cgm include: phase-locked loop with output frequency in integer multiples of the crystal reference programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 5.3 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal oscillator circuit generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk. base clock selector circuit ? this so ftware-controlled circuit selects either cgmxclk divided by two or the vco cl ock, cgmvclk, divided by two as the base clock, cgmout. the sim derives the system clocks from cgmout. figure 5-1 shows the structure of the cgm.
data sheet mc68hc08as32 ? rev. 4.1 90 freescale semiconductor figure 5-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim, sci, adc, bdlc to sim ptc3 monitor mode a b s* user mode *when s = 1, cgmout = b
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 91 5.3.1 crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input and the osc2 pin is the output to the amplifier. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to th e osc1 pin and let the osc2 pin float. 5.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that c an operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. while reading this section, refer to 17.8 cgm operating conditions for operating frequencies. addr. register name bit 7654321bit 0 $001c pll control register (pctl) see page 99. read: pllie pllf pllon bcs 1111 write: r rrrr reset:00101111 $001d pll bandwidth control register (pbwc) see page 100. read: auto lock acq xld 0000 write: r rrrr reset:00000000 $001e pll programming register (ppg) see page 102. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 r=reserved notes: 1. when auto = 0, pllie is forced to logic 0 and is read-only. 2. when auto = 0, pllf and lock read as logic 0. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[ 7:4] = $0, bcs is forced to logic 0 and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 5-2. cgm i/o register summary
data sheet mc68hc08as32 ? rev. 4.1 92 freescale semiconductor 5.3.2.1 circuits the pll consists of these circuits: voltage-controlled oscillator (vco) modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external no ise, including supply and cgmxfc noise. (for maximum immunity gui delines on electromagnetic compatibility, refer to document numbers an1050/d and an1263/d av ailable from your freescale sales office.) the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , 4.9152 mhz times a linear factor (l) or f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a crystal frequency, f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency equal to f rclk . the vco?s output clock, cgmvclk, running at a frequency, f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor, n (see 5.3.2.4 programming the pll ). the divider?s output is the vco feedback clock, cgmvdv, running at a frequency equal to f vclk /n. see 17.8 cgm operating conditions for more information. the phase detector then compares the vco feedback clock (cgmvdv) with the final reference clock (cgmrdv). a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to cgmxfc, based on the width and direction of the correction pulse. the filter can make fast or slow corrections, depending on its mode, described in 5.3.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequenc ies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to th e final reference frequency, f rd . the circuit determines the mode of the pll and the lock condition based on this comparison.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 93 5.3.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ? in acquisition mode, the filter can make large (see 17.10 cgm acquisition/lock time information ) frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 5.5.2 pll bandwidth control register .) tracking mode ? in tracking mode, the filter makes only small (see 17.10 cgm acquisition/lock time information ) corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 5.3.3 base clock selector circuit .) the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. 5.3.2.3 automatic and manual pll bandwidth modes the pll can change the bandwidth or operati onal mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the vc o clock, cgmvclk, is safe to use as the source for the base clock, cgmout. (see 5.5.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll start up, usually) or at periodic intervals. in either case, when the lock bit is set, t he vco clock is safe to use as the source for the base clock. (see 5.3.3 base clock selector circuit .) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. (see 5.6 interrupts for information and precautions on using interrupts.) the following conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 5.5.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. (see 5.3.2.2 acquisition and tracking modes .) the acq bit is set when the vco frequency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . (see 5.9 acquisition/lock time specifications for more information.)
data sheet mc68hc08as32 ? rev. 4.1 94 freescale semiconductor the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . (see 5.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 5.5.1 pll control register .) the pll also can operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 5.9 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 5.3.2.4 programming the pll use this procedure to program the pll: 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . f vclkdes = 4 f busdes example: f vclkdes = 4 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. note: the round function means that the result is rounded to the nearest integer. example: n round f vclkdes f rclk ---------------------- ?? ?? = n 32 mhz 4 mhz -------------------- =8 =
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 95 4. calculate the vco frequency, f vclk . example: f vclk = 8 4 mhz = 32 mhz 5. calculate the bus frequency, f bus , and compare f bus with f busdes . if the calculated f bus is not within the tolerance limi ts of your application, select another f busdes or another f rclk . example: 6. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. example: 7. calculate the vco center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f vrs = l f nom example: f vrs = 7 4.9152 mhz = 34.4 mhz note: exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. for proper operation, 8. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. f vclk nf rclk = f bus f vclk 4 -------------- = f bus 32 mhz 4 -------------------- =8 mhz = l round f vclk f nom ------------- ?? ?? = l 32 mhz 4.9152 mhz ------------------------------- - = 7 = f vrs f vclk ? f nom 2 ------------ -
data sheet mc68hc08as32 ? rev. 4.1 96 freescale semiconductor 5.3.2.5 special programming exceptions the programming method described in 5.3.2.4 programming the pll does not account for two possible exceptions. a val ue of zero for n or l is meaningless when used in the equations given. to account for these exceptions: a zero value for n is interpreted exactly the same as a value of one. a zero value for l disables the pll and prevents its selection as the source for the base clock. (see 5.3.3 base clock selector circuit .) 5.3.3 base clock selector circuit this circuit is used to select either the crystal clock (cgmxclk) or the vco clock (cgmvclk) as the source of the base clock (cgmout). the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a ze ro. this value woul d set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. 5.3.4 cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 5-3 . figure 5-3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 , can also be a fixed capacitor feedback resistor, r b series resistor, r s , optional
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 97 the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for a ll ranges of operation, especially with high-frequency crystals. refer to the cr ystal manufacturer?s data for more information. figure 5-3 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f routing should be done with great care to minimize signal cross talk and noise. (see 5.9 acquisition/lock time specifications for routing information and more information on the filter capacitor?s value and its effects on pll performance.) figure 5-3. cgm external connections 5.4 i/o signals the following paragraphs describe the cgm input/output (i/o) signals. 5.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 5.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc2 v ss cgmxfc v dda /v ddaref *r s can be 0 (shorted) when used with higher-fre quency crystals. refer to manufacturer?s data. v dd
data sheet mc68hc08as32 ? rev. 4.1 98 freescale semiconductor 5.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. 5.4.4 analog power pin (v dda /v ddaref ) v dda /v ddaref is a power pin used by the analog portions of the pll. connect the v dda /v ddaref pin to the same voltage potential as the v dd pin. note: route v dda /v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 5.4.5 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator and pll. 5.4.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal, f xclk , and comes directly from the crystal oscillator circuit. figure 5-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the dut y cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 5.4.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software pr ogrammable to be either the oscillator output, cgmxclk, divided by two or th e vco clock, cgmvclk, divided by two. 5.4.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 99 5.5 cgm registers these registers control and monitor operation of the cgm: pll control register (pctl) (see 5.5.1 pll control register .) pll bandwidth control register (pbwc) (see 5.5.2 pll bandwidth control register .) pll programming register (ppg) (see 5.5.3 pll programming register .) figure 5-2 is a summary of the cgm registers. 5.5.1 pll control register the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently clear the pllf bit. an y read or read-modify-write operation on the pll control register clears the pllf bit. address: $001c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: r rrrr reset:00101111 r= reserved figure 5-4. pll control register (pctl)
data sheet mc68hc08as32 ? rev. 4.1 100 freescale semiconductor pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco cloc k is driving the base clock, cgmout (bcs = 1). (see 5.3.3 base clock selector circuit .) reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk cycles and three cgmvclk cycl es to complete the transition from one source clock to the other. during the transition, cgmout is held in stasis. (see 5.3.3 base clock selector circuit .) reset and the stop instruction clear the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see 5.3.3 base clock selector circuit .) pctl[3:0] ? unimplemented bits these bits provide no function and always read as logic 1s. 5.5.2 pll bandwidth control register the pll bandwidth control register: selects automatic or manual (softwar e-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode address: $001d bit 7654321bit 0 read: auto lock acq xld 0000 write: r rrrr reset:00000000 r= reserved figure 5-5. pll bandwidth control register (pbwc)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 101 auto ? automatic ba ndwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mo de. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition mode or tracking mode. in automatic bandwidth control mode (aut o = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output (cgmvclk) is driv ing cgmout, this read/write bit can indicate whether the crystal reference frequency is active or not. to check the status of the crystal reference, follow these steps: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vco frequency multiplier.) 3. read xld. 1 = crystal reference not active 0 = crystal reference active the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as logic 0. pbwc[3:0] ? reserved for test these bits enable test functions not avai lable in user mode. to ensure software portability from development systems to user applications, software should write 0s to pbwc[3:0] whenever writing to pbwc.
data sheet mc68hc08as32 ? rev. 4.1 102 freescale semiconductor 5.5.3 pll programming register the pll programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] ? multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. (see 5.3.2 phase-locked loop circuit (pll) .) a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs[7:4] ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier, l, which controls the hardware center-of-range frequency, f vrs , (see 5.3.2 phase-locked loop circuit (pll) ). vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see 5.3.2.5 special programming exceptions .) a value of $0 in the vco range selects bits, disables the pll, and clears the bcs bit in the pctl. (see 5.3.3 base clock address: $001e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 5-6. pll programming register (ppg) table 5-1. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco fr equency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 103 selector circuit and 5.3.2.5 special programming exceptions for more information.) reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in prot ection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be pr ogrammed correctly. incorrect programming can result in failure of the pll to achieve lock. 5.6 interrupts when the auto bit is set in the pll band width control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding so ftware performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 5.7 special modes the wait and stop instructions put the mcu in low-power standby modes. 5.7.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselec t the pll output without turning off the pll.
data sheet mc68hc08as32 ? rev. 4.1 104 freescale semiconductor 5.7.2 stop mode when the stop instruction executes, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock (cgmvclk) divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the cr ystal clock (cgmxclk) divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. 5.8 cgm during break interrupts the system integration module (sim) contro ls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 13.7.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 5.9 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure the highest stability and lowest acquisition/lock times. 5.9.1 acquisition/lock time definitions typical control systems refer to the acquisi tion time or lock time as the reaction time, within specified toler ances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance usually is specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change fr om 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. 50 khz = 5% of the 1-mhz step input. if the system is operati ng at 1 mhz and suffers a ?100-khz noise hit, the acquisition time is the time ta ken to return from 900 khz to 1 mhz 5khz. 5 khz = 5% of the 100-khz step input.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 105 other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisiti on time or lock time vary according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this def inition because the system requires the output frequency to be within a cert ain tolerance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, t he definitions for acquisition and lock times for this module are: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, [(f des ? f orig )/f des ], of not more than 100%. in automatic bandwidth control mode (see 5.3.2.3 automatic and manual pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). lock time, t l ock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ? l ock . lock time is based on an initial frequency error, [(f des ? f orig )/f des ], of not more than 100%. in automatic bandwidth control mode, lock time ex pires when the lock bit becomes set in the pll bandwidth control register (pbwc). (see 5.3.2.3 automatic and manual pll bandwidth modes .) obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 5.9.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the pll reaction times is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of an external crystal frequency, f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related
data sheet mc68hc08as32 ? rev. 4.1 106 freescale semiconductor to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 5.9.3 choosing a filter capacitor .) also important is the operating voltage potential applied to the pll analog portion potential (v dda /v ddaref ). typically, v dda /v ddaref is at the same potential as v dd . the power supply potential alters the c haracteristics of the pll. a fixed value is best. variable supplies, such as batteries , are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limi ts. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 5.9.3 choosing a filter capacitor as described in 5.9.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency, f rdv , and supply voltage, v dd . the value of the capacitor, therefore, must be chosen with supply potential and reference frequency in mind. for proper operation, the exte rnal filter capacitor must be chosen according to the following equation. refer to 5.3.2 phase-locked loop circuit (pll) for the value of f rdv and 17.9 cgm component information for the value of c fact . for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a comm only available capac itor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing t he lower size may seem attractive for acquisition time improvement, but the pl l can become unstable. also, always choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. c f c fact v dda f rdv ------------- ?? ?? =
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 107 5.9.4 reaction time calculation the actual acquisition and lock times can be calculated using the equations in this subsection. these equations yield nomin al values under the following conditions: correct selection of filter capacitor, c f (see 5.9.3 choosing a filter capacitor .) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is conf igured in acquisition mode, and k trk is the k factor when the pll is configur ed in tracking mode. (see 5.3.2.2 acquisition and tracking modes .) note: there is an inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode, th e acquisition and lock times are quantized into units based on the reference frequency. (see 5.3.2.3 automatic and manual pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. additionally, a certain number of clock cycles, n trk , is required to ascertain that the pll is wi thin the lock mode entry tolerance, ? l ock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . refer to 5.3.2 phase-locked loop circuit (pll) for the value of f rdv . also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t l ock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t l ock before selecting the pll clock (see 5.3.3 base clock selector circuit ), because the factors described in 5.9.2 parametric influences on reaction time can slow the lock time considerably. t acq v dda f rdv ------------- ?? ?? 8 k acq ------------- ?? ?? = t al v dda f rdv ------------- ?? ?? 4 k trk ------------ - ?? ?? = t lock t acq t al + =
data sheet mc68hc08as32 ? rev. 4.1 108 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 109 data sheet ? mc68hc08as32 section 6. computer op erating properly (cop) 6.1 introduction this section describes the computer operating properly (cop) module, a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter. 6.2 functional description figure 6-1 shows the structure of the cop module. the cop counter is a free-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. cop ti meouts are determined strictly by the cgm crystal oscillator clock signal (c gmxclk), not the cgmout signal (see figure 5-1. cgm block diagram ). if not cleared by software, the cop counter overflows and generates an asynchronous reset after (2 13 ? 2 4 ) or (2 18 ? 2 4 ) cgmxclk cycles, depending upon cops bit in the mor register ($001f) (see section 10. mask options .) with a 4.9152-mhz crystal and the cops bit in the mor register ($001f) set to a logic 1, the cop timeout period is approx imately 53.3 ms. writing any value to location $ffff before overflow occurs clears the cop counter, clears bits 12 through 4 of the sim counter, and prevents reset. a cpu interrupt routine can be used to clear the cop. note: the cop should be serviced as soon as possible out of reset and before entering or after exiting stop mode to guarantee the maximum selected amount of time before the first timeout. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr) (see 13.7.2 sim reset status register ). while the microcontroller is in monitor mo de, the cop module is disabled if the rst pin or the irq pin is held at v dd + v hi (see 17.4 5.0-volt dc electrical characteristics ). during a break state, v dd + v hi on the rst pin disables the cop module. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subrouti ne could keep the cop from generating a reset even while the main program is not working properly. the one exception to this is wait mode (see 6.7.1 wait mode ).
data sheet mc68hc08as32 ? rev. 4.1 110 freescale semiconductor figure 6-1. cop block diagram 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cgmxclk frequency is equal to the crystal frequency. 6.3.2 stop instruction the stop instruction clears the sim counter. copctl write cgmxclk reset vector fetch sim reset circuit sim reset status register internal reset sources (1) stop instruction sim clear bits 12?4 12-bit sim counter clear all bits 6-bit cop counter copd (from mor) reset copctl write clear cop module copen (from sim) cop counter 1. see 13.3.2 active resets from internal sources . cops
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 111 6.3.3 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears bits 12 through 4 of the sim counter. reading the cop control register returns the reset vector. 6.3.4 internal reset resources an internal reset clears the sim counter and the cop counter. (see 13.3.2 active resets from internal sources .) 6.3.5 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the sim counter. 6.3.6 copd (cop disable) the copd bit reflects the state of the co p disable bit (copd) in the mor register ($001f). this signal disables cop- generated resets when asserted. (see section 10. mask options .) 6.3.7 cops (cop short timeout) the cops bit selects the state of the cop short timeout bit (cops) in the mor register ($001f). timeout periods can be (2 18 ?2 4) or (2 13 ?2 4) cgmxclk cycles. (see 10.3 mask option register .) 6.4 cop cont rol register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl)
data sheet mc68hc08as32 ? rev. 4.1 112 freescale semiconductor 6.6 monitor mode the cop is disabled in monitor mode when v dd +v hi (see 17.4 5.0-volt dc electrical characteristics ) is present on the irq pin or on the rst pin. 6.7 low-power modes the following subsections des cribe the low-power modes. 6.7.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. note: if the cop is enabled in wait mode, it must be periodically refreshed. (see 6.3.6 copd (cop disable) .) 6.7.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the mor register ($001f) (see section 10. mask options ) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by programming the stop bit to logic 0. 6.8 cop module duri ng break interrupts the cop is disabled during a break interrupt when v dd +v hi (see 17.4 5.0-volt dc electrical characteristics ) is present on the rst pin.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 113 data sheet ? mc68hc08as32 section 7. central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processo r unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes
data sheet mc68hc08as32 ? rev. 4.1 114 freescale semiconductor 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the re sults of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 115 7.3.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regist er, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes , the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack point er decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an i ndex register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp)
data sheet mc68hc08as32 ? rev. 4.1 116 freescale semiconductor 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automati cally increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 117 h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, t he highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7
data sheet mc68hc08as32 ? rev. 4.1 118 freescale semiconductor 7.4 arithmetic/ logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from st op mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 119 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 c b0 b7 0 b0 b7 c
data sheet mc68hc08as32 ? rev. 4.1 120 freescale semiconductor bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 table 7-1. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 121 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 table 7-1. instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
data sheet mc68hc08as32 ? rev. 4.1 122 freescale semiconductor dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 123 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 table 7-1. instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 c b0 b7 b0 b7 c
data sheet mc68hc08as32 ? rev. 4.1 124 freescale semiconductor rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 table 7-1. instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 125 7.8 opcode map see table 7-2 . tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
data sheet mc68hc08as32 ? rev. 4.1 126 freescale semiconductor table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 127 data sheet ? mc68hc08as32 section 8. external interrupt (irq) 8.1 introduction this section describes the non-maskable external interrupt (irq) input. 8.2 features features of the irq include: dedicated external interrupt pin (irq ) hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge 8.3 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 8-1 shows the structure of the irq module. figure 8-1. irq block diagram ack imask dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus
data sheet mc68hc08as32 ? rev. 4.1 128 freescale semiconductor figure 8-2. block diagram highlighting the irq block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 129 interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to t he ack bit clears the irq latch. reset ? a reset automatically clears both interrupt latches. the external interrupt pin is falling-e dge triggered and is software configurable to be both falling-edge and low-level triggered. the mode bit in the iscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level triggered, the interrupt latch remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr mask s all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the corresponding imask bit is clear. note: the interrupt mask (i) in the condition c ode register (ccr) masks all interrupt requests, including external interrupt requests. (see figure 8-4 .) addr. register name bit 7 6 5 4 3 2 1 bit 0 $001a irq status and control register (iscr) see page 132. read: 0 0 0 0 irqf 0 imask mode1 write: r r r r r ack1 reset:000 0 0000 r= reserved figure 8-3. irq i/o register summary
data sheet mc68hc08as32 ? rev. 4.1 130 freescale semiconductor figure 8-4. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction. swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 131 8.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of the fo llowing actions must occur to clear the irq latch: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge on irq that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq latch remains set. the vector fetch or software clear and the return of the irq pin to logic 1 can occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge sens itive only. with mode clear, a vector fetch or software cl ear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 8.5 irq module during break interrupts the system integration module (sim) cont rols whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. (see 13.7.3 sim break flag control register .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state.
data sheet mc68hc08as32 ? rev. 4.1 132 freescale semiconductor to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 8.6 irq status an d control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr: shows the state of the irq interrupt flag clears the irq interrupt latch masks irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001a bit 7654321bit 0 read:0000irqf0 imask mode write:rrrrrack reset:00000000 r= reserved figure 8-5. irq status and control register (iscr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 133 data sheet ? mc68hc08as32 section 9. low-volt age inhibit (lvi) 9.1 introduction this section describes the low-voltage i nhibit module (lvi), which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 9.2 features features of the lvi module include: programmable lvi reset programmable power consumption digital filtering of v dd pin level 9.3 functional description figure 9-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, v lvif , and remains at or below that level for nine or more consecutive cpu cycles. lvistop, enables th e lvi module during stop mode. this will ensure when the stop instruction is implemented, the lvi will continue to monitor the voltage level on v dd . lvipwr, lvistop, and lvirst are in the mor register ($001f) (see section 10. mask options ). once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v lvir . the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices.
data sheet mc68hc08as32 ? rev. 4.1 134 freescale semiconductor figure 9-1. lvi module block diagram 9.3.1 polled lvi operation in applications that can operate at v dd levels below the v lvif level, software can monitor v dd by polling the lviout bit. in the mor register, the lvipwr bit must be at logic1 to enable the lvi module, and the lvirst bit must be at logic 0 to disable lvi resets. 9.3.2 forced reset operation in applications that require v dd to remain above the v lvif level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the v lvif level and remains at or below that level for ni ne or more consecutive cpu cycles. in the mor register, the lvipwr and lvirst bits must be at logic 1 to enable the lvi module and to enable lvi resets. 9.3.3 false reset protection the v dd pin level is digitally filtered to r educe false resets du e to power supply noise. in order for the lv i module to reset the mcu,v dd must remain at or below the v lvif level for nine or more consecutive cpu cycles. v dd must be above v lvir for only one cpu cycle to bring the mcu out of reset. low v dd lvirst v dd > v lvir = 0 v dd < v lvif = 1 lviout lvipwr detector v dd lvi reset from config from config v dd digital filter cpu clock anlgtrip stop mode filter bypass lvistop from config
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 135 9.4 lvi status register the lvi status register flags v dd voltages below the v lvif level. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v lvif voltage or 32 to 40 cgmxclk cycles. (see table 9-1 .) reset clears the lviout bit. 9.5 lvi interrupts the lvi module does not generate interrupt requests. 9.6 low-power modes the stop and wait instructions put the mcu in low-power standby modes. 9.6.1 wait mode with the lvipwr bit in the mor register programmed to logic 1, the lvi module is active after a wait instruction. with the lvirst bit in the mor register programmed to logic 1, the lvi module can generate a reset and bring the mcu out of wait mode. address: $fe0f bit 7654321bit 0 read:lviout0000000 write:rrrrrrrr reset:00000000 r= reserved figure 9-2. lvi status register (lvisr) table 9-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > v lvir any 0 v dd < v lvif < 32 cgmxclk cycles 0 v dd < v lvif between 32 and 40 cgmxclk cycles 0 or 1 v dd < v lvif > 40 cgmxclk cycles 1 v lvif < v dd < v lvir any previous value
data sheet mc68hc08as32 ? rev. 4.1 136 freescale semiconductor 9.6.2 stop mode with the lvistop and lvipwr bits in t he configuration register programmed to a logic 1, the lvi module will be active after a stop instruction. because cpu clocks are disabled during stop mode, the lvi trip must bypass the digital filter to generate a reset and bring the mcu out of stop. with the lvipwr bit in the mor register programmed to logic 1 and the lvistop bit at a logic 0, the lvi module will be inactive a fter a stop instruction. note: if the lvipwr bit is at logic 1, the lvis top bit must be at logic 0 to meet the minimum stop mode i dd specification.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 137 data sheet ? mc68hc08as32 section 10. mask options 10.1 introduction this section describes use of mask opti ons by custom-masked read-only memory (roms) and the mask option register in the mc68hc08as32. 10.2 functional description the mask options are hard-wired connections, specified at the same time as the rom code, which allow the user to customize the mcu. the options control the enable or disable ability of the following functions: rom security (1) resets caused by the lvi module power to the lvi module stop mode recovery time (32 cgmx clk cycles or 4096 cgmxclk cycles) cop timeout period (2 18 ?2 4 cgmxclk cycles or 2 13 ?2 4 cgmxclk cycles) stop instruction computer operating properly module (cop) the mask option register ($001f) is used in the initialization of various options. for error free compatibility with the emulator otp (m68hc908at32cfn), a write to $001f in the mc68hc08as32 has no effect in mcu operation. 10.3 mask opti on register 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the rom data difficu lt for unauthorized users. address: $001f bit 7654321bit 0 read: lvistop romsec lvirst lvipwr ssrec coprs stop copd write:rrrrrrrr reset: unaffected by reset r= reserved figure 10-1. mask option register (mor)
data sheet mc68hc08as32 ? rev. 4.1 138 freescale semiconductor lvistop ? lvi stop mode enable bit lvistop enables the lvi module in stop mode.(see section 9. low-voltage inhibit (lvi) .) 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode romsec ? rom security bit romsec enables the rom security featur e. setting the romsec bit prevents reading of the rom contents. access to the rom is denied to unauthorized users of customer-specified software. 1 = rom security enabled 0 = rom security disabled lvirst ? lvi reset enable bit lvirst enables the reset signal from the lvi module. (see section 9. low-voltage inhibit (lvi) .) 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr enables the lvi module. (see section 9. low-voltage inhibit (lvi) .) 1 = lvi module power enabled 0 = lvi module power disabled ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. (see 15.5.2 stop mode .) 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note: if using an external crystal osci llator, do not set the ssrec bit. coprs ? cop rate select timeout bit cops selects the short cop timeout period. (see section 6. computer operating properly (cop) .) 1 = cop timeout period is 2 13 ?2 4 cgmxclk cycles. 0 = cop timeout period is 2 18 ?2 4 cgmxclk cycles. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 6. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 139 data sheet ? mc68hc08as32 section 11. input/output (i/o) ports 11.1 introduction forty bidirectional input/output (i/o) pins form six parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termin ation for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 140. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 142. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 144. read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r r reset: unaffected by reset $0003 port d data register (ptd) see page 146. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r reset: unaffected by reset $0004 data direction register a (ddra) see page 141. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 143. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 145. read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r r reset: 0 0 0 0 0 0 0 0 r = reserved figure 11-1. i/o port register summary
data sheet mc68hc08as32 ? rev. 4.1 140 freescale semiconductor 11.2 port a port a is an 8-bit general-purpose bidirectional i/o port. 11.2.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software progra mmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. $0007 data direction register d (ddrd) see page 147. read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 write: r reset: 0 0 0 0 0 0 0 0 $0008 port e data register (pte) see page 149. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 151. read: 0 0 0 0 ptf3 ptf2 ptf1 ptf0 write: r r r r reset: unaffected by reset $000c data direction register e (ddre) see page 150. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000d data direction register f (ddrf) see page 153. read: 0 0 0 0 ddrf3 ddrf2 ddrf1 ddrf0 write: r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved figure 11-1. i/o port register summary (continued) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 11-2. port a data register (pta)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 141 11.2.2 data direction register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 11-4 shows the port a i/o logic. figure 11-4. port a i/o circuit when bit ddrax is a logic 1, reading add ress $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-1 summarizes the operation of the port a pins. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 11-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
data sheet mc68hc08as32 ? rev. 4.1 142 freescale semiconductor 11.3 port b port b is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (adc). 11.3.1 port b data register the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software progra mmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. atd[7:0] ? adc channels ptb7/atd7?ptb0/atd0 are eight of the 15 analog-to-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptb7/atd7?ptb0/atd0 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. (see section 3. analog-to-digital converter (adc) .) data direction register b (ddrb) does not affect the data direction of port b pins that are being used by the adc. however, the ddrb bi ts always determine whether reading port b returns to the states of the latches or logic 0. table 11-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x input, hi-z ddra[7:0] pin pta[7:0] (1) 1 x output ddra[7:0] pta[7:0] pta[7:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate functions: atd7 atd6 atd5 atd4 atd3 atd2 atd1 atd0 figure 11-5. port b data register (ptb)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 143 11.3.2 data direction register b data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 11-7 shows the port b i/o logic. figure 11-7. port b i/o circuit when bit ddrbx is a logic 1, reading add ress $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin, or logic 0 if that particular bit is in use by the adc. the data latch can always be written, regardless of the state of its data direction bit. table 11-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 11-6. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
data sheet mc68hc08as32 ? rev. 4.1 144 freescale semiconductor 11.4 port c port c is a 5-bit general-purpose bidirectional i/o port that shares one of its pins with the bus clock (mclk). 11.4.1 port c data register the port c data register contains a data latch for each of the five port c pins. ptc[4:0] ? port c data bits these read/write bits are software-program mable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. mclk ? t12 system bus clock bit the bus clock (mclk) is driven out of ptc2 when enabled by the mclken bit in ptcddr7. table 11-2. port b pin functions ddrb bit ptb bit bit in use by adc i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x no input, hi-z ddrb[7:0] pin ptb[7:0] (1) 1 x no output ddrb[7:0] ptb[7:0] ptb[7:0] 0 x yes input, hi-z ddrb[7:0] 0 ptb[7:0] (1) 1 x yes input, hi-z ddrb[7:0] ptb[7:0] ptb[7:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input. address: $0002 bit 7654321bit 0 read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write:rrr reset: unaffected by reset r= reserved alternate functions: mclk figure 11-8. port c data register (ptc)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 145 11.4.2 data direction register c data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. mclken ? mclk enable bit this read/write bit enables mclk to be an output signal on ptc2. if mclk is enabled, ptc2 is under the control of mclken. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled ddrc[4:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writi ng to the port c data register before changing data direction register c bits from 0 to 1. figure 11-10 shows the port c i/o logic. figure 11-10. port c i/o circuit address: $0006 bit 7654321bit 0 read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r r reset:00000000 r= reserved figure 11-9. data direction register c (ddrc) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
data sheet mc68hc08as32 ? rev. 4.1 146 freescale semiconductor when bit ddrcx is a logic 1, reading add ress $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading add ress $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-3 summarizes the operation of the port c pins. 11.5 port d port d is an 8-bit special-function i/o port that shares all of its pins with the analog-to-digital converter (adc). 11.5.1 port d data register the port d data register contains a data latch for the seven port d pins. ptd[6:0] ? port d data bits ptd[6:0] are read/write, software programmable bits. data direction of ptd[6:0] pins are under the control of the corresponding bit in data direction register d. table 11-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write [7] = 0 ptc2 input, hi-z ddrc[7] 0 ptc2 [7] = 1 ptc2 output, mclk ddrc[7] data latch ? 0 x input, hi-z ddrc[4:0] pin ptc[4:3, 1:0] (1) 1 x output ddrc[4:0] ptc[4:0] ptc[4:3, 1:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input. address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r reset: unaffected by reset alternate functions: r atd14/ tclk atd13 atd12 atd11 atd10 atd9 atd8 r= reserved figure 11-11. port d data register (ptd)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 147 atd[14:8] ? adc channel status bits ptd6/atd14/tclk?ptd0/atd8 are seven of the 15 analog-to-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptd6/atd14/tclk?ptd0/atd8 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. (see section 3. analog-to-digital converter (adc) .) note: data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the adc. however, the ddrd bits always determine whether reading port d returns the states of the latches or logic 0. tclk ? timer clock input bit the ptd6/atd14/tclk pin is the external clock input for the tim. the prescaler select bits, ps[2:0], select ptd6/atd14/tclk as the tim clock input. (see 15.8.1 tim status and control register .) when not selected as the tim clock, ptd6/atd14/tclk is available for general-purpose i/o or as an adc channel. note: do not use adc channel atd14 when us ing the ptd6/atd14/tclk pin as the clock input for the tim. 11.5.2 data direction register d data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. ddrd[6:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[6:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writi ng to the port d data register before changing data direction register d bits from 0 to 1. figure 11-13 shows the port d i/o logic. address: $0007 bit 7654321bit 0 read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: 0 reset:00000000 figure 11-12. data direction register d (ddrd)
data sheet mc68hc08as32 ? rev. 4.1 148 freescale semiconductor figure 11-13. port d i/o circuit when bit ddrdx is a logic 1, reading add ress $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading add ress $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-4 summarizes the operation of the port d pins. table 11-4. port d pin functions ddrd bit ptd bit bit in use by adc i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x no input, hi-z ddrd[6:0] pin ptd[6:0] (1) 1 x no output ddrd[6:0] ptd[6:0] ptd[6:0] 0 x yes input, hi-z ddrd[6:0] 0 ptd[6:0] (1) 1 x yes input, hi-z ddrd[6: 0] ptd[6:0] ptd[6:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 149 11.6 port e port e is an 8-bit special-function port that shares two of its pins with the timer interface module (tim), two of its pins with the serial communications interface module (sci), and four of its pins with t he serial peripheral interface module (spi). 11.6.1 port e data register the port e data register contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. spsck ? spi serial clock bit the pte7/spsck pin is the serial clock input of an spi slave module and serial clock output of an spi master modul e. when the spe bit is clear, the pte7/spsck pin is availabl e for general-purpose i/o. mosi ? master out/slave in bit the pte6/mosi pin is the master out/slave in terminal of the spi module. when the spe bit is clear, the pte6/mosi pi n is available for general-purpose i/o. (see 14.13.1 spi control register .) miso ? master in/slave out bit the pte5/miso pin is the master in/slave out terminal of the spi module. when the spi enable bit, spe, is clear, t he spi module is disabled, and the pte5/miso pin is available for general-purpose i/o. (see 14.13.1 spi control register .) ss ? slave select bit the pte4/ss pin is the slave select input of the spi module. when the spe bit is clear or when the spi master bit, spmst r, is set and modfen bit is low, the pte4/ss pin is available for general-purpose i/o. (see 14.12.4 ss (slave select) .) when the spi is enabled as a slave, the ddre4 bit in data direction register e (ddre) has no effect on the pte4/ss pin. note: data direction register e (ddre) does not af fect the data direction of port e pins that are being used by the spi module. ho wever, the ddre bits always determine address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternate function: spsck mosi miso ss tch1 tch0 rxd txd figure 11-14. port e data register (pte)
data sheet mc68hc08as32 ? rev. 4.1 150 freescale semiconductor whether reading port e returns the states of the latches or the states of the pins. (see table 11-5 .) tch[1:0] ? timer channel i/o bits the pte3/tch1?pte2/tch0 pins are t he tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pte3/tch1?pte2/tch0 pins are timer channel i/o pins or general-purpose i/o pins. (see 15.8.4 tim channel status and control registers .) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. ho wever, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 11-5 .) rxd ? sci receive data input bit the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sc i module is disabled, and the pte1/rxd pin is available for general-purpose i/o. (see 12.8.1 sci control register 1 .) txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. (see 12.8.1 sci control register 1 .) note: data direction register e (ddre) does not af fect the data direction of port e pins that are being used by the sci module. ho wever, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 11-5 .) 11.6.2 data direction register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] ? data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 11-15. data direction register e (ddre)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 151 note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 11-16 shows the port e i/o logic. figure 11-16. port e i/o circuit when bit ddrex is a logic 1, reading add ress $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-5 summarizes the operation of the port e pins. table 11-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x input, hi-z ddre[7:0] pin pte[7:0] (1) 1 x output ddre[7:0] pte[7:0] pte[7:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input. read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
data sheet mc68hc08as32 ? rev. 4.1 152 freescale semiconductor 11.7 port f port f is a 4-bit special-function port that shares four of its pins with the timer interface module (tim). 11.7.1 port f data register the port f data register contains a data latch for each of the four port f pins. ptf[3:0] ? port f data bits these read/write bits are software progr ammable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on ptf[3:0]. tch[5:2] ? timer channel i/o bits the ptf3/tch5?ptf0/tch2 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb?elsxa, determine whether the ptf3/tch5?ptf0/tch2 pins are timer channel i/o pins or general-purpose i/o pins. (see 15.8.4 tim channel status and control registers .) note: data direction register f (ddrf) does not affect the data direction of port f pins that are being used by the tim. ho wever, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. (see table 11-6 .) address: $0009 bit 7654321bit 0 read:0000 ptf3 ptf2 ptf1 ptf0 write:rrrr reset: unaffected by reset alternate function: tch5 tch4 tch3 tch2 r= reserved figure 11-17. port f data register (ptf)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 153 11.7.2 data direction register f data direction register f determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logic 0 disables the output buffer. ddrf[3:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[3:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. figure 11-19 shows the port f i/o logic. figure 11-19. port f i/o circuit when bit ddrfx is a logic 1, reading address $0009 reads the ptfx data latch. when bit ddrfx is a logic 0, reading addres s $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-6 summarizes the operation of the port f pins. address: $000d bit 7654321bit 0 read:0000 ddrf3 ddrf2 ddrf1 ddrf0 write:rrrr reset:00000000 r= reserved figure 11-18. data direction register f (ddrf) read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus
data sheet mc68hc08as32 ? rev. 4.1 154 freescale semiconductor table 11-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x input, hi-z ddrf[3:0] pin ptf[3:0] (1) 1 x output ddrf[3:0] ptf[3:0] ptf[3:0] x = don?t care hi-z = high impedance 1. writing affects data regist er, but does not affect input.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 155 data sheet ? mc68hc08as32 section 12. serial commun ications inte rface (sci) 12.1 introduction this section describes the serial communications interface module (sci, version d), which allows high-speed asynchronous communications with peripheral devices and other mcus. 12.2 features features of the sci module include: full duplex operation standard mark/space non-return-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection
data sheet mc68hc08as32 ? rev. 4.1 156 freescale semiconductor figure 12-1. block diagram highlighting sci block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 157 12.3 functional description figure 12-3 shows the structure of the sci module. the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) see page 170. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 172. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 174. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 175. read: scte tc scrf idle or nf fe pe write:rrr r rrrr reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 178. read: 0 0 0 0 0 0 bkf rpf write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 179. read:r7r6r5 r4 r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 179. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 r = reserved u = unaffected figure 12-2. sci i/o register summary
data sheet mc68hc08as32 ? rev. 4.1 158 freescale semiconductor figure 12-3. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci pte1/rxd pte0/txd internal bus txinv loops 4 16 pre- scaler baud rate generator cgmxclk
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 159 12.3.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 12-4 . figure 12-4. sci data formats 12.3.2 transmitter figure 12-5 shows the structure of the sci transmitter. 12.3.3 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 12.3.4 character transmission during an sci transmission, the transmit shi ft register shifts a character out to the pte0/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift r egister. to initiate an sci transmission: 1. initialize the tx and rx rate in the sci baud register (scbr) ($0019) see 12.8.7 sci baud rate register . 2. enable the sci by writing a logic 1 to ensci in sci control register 1 (scc1) ($0013). 3. enable the transmitter by writing a l ogic 1 to the transmitter enable bit (te) in sci control register 2 (scc2) ($0014). 4. clear the sci transmitter empty bit (scte) by first reading sci status register (scs1) ($0016) and then writing to the scdr ($0018). 5. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitte r control logic automatically loads the transmit shift register with a preamble of 10 or 11 logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes in to the most significant bit position. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit
data sheet mc68hc08as32 ? rev. 4.1 160 freescale semiconductor the sci transmitter empty bit, scte in t he sci status control register (scs1), becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sc tie (scc2), is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitte r and receiver relinquish control of the port e pins. figure 12-5. sci transmitter pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc cgmxclk parity generation msb sci data register load from scdr shift enable preamble all ones break all zeros transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te pte0/txd txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 161 12.3.5 break characters writing a logic 1 to the send break bit, sbk (scc2), loads the trans mit shift register with a break character. a break characte r contains all logic 0s and has no start, stop, or parity bit. break character le ngth depends on the m bit (scc1). as long as sbk is at logic 1, transmitte r logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break c haracter guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has the following effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 12.3.6 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit (m ode character length) in scc1. the preamble is a synchronizing idle c haracter that begins every transmission. if the te bit (transmitter enable) is cleared during a transmission, the pte0/txd pin becomes idle after completion of the tr ansmission in progress. clearing and then setting the te bit during a transmission qu eues an idle character to be sent after the character currently being transmitted. note: when a break sequence is followed immediat ely by an idle character, this sci design exhibits a condition in which the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or nine data bits (as defined by the m bit in scc1) of logic 0, and one half data bit length of logic 0 in the stop bit position followed immediately by the idle character. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the pte0 /txd pin. setting te after the stop bit appears on pte0/txd causes loss of data previously written to the scdr.
data sheet mc68hc08as32 ? rev. 4.1 162 freescale semiconductor a good time to toggle the te bit is w hen the scte bit becomes set and just before writing the next byte to the scdr. 12.3.7 inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transm itted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 12.8.1 sci control register 1 .) 12.3.8 transmitter interrupts the following conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to t he transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie (scc2), enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the tr ansmission complete interrupt enable bit, tcie (scc2), enables the tc bit to generate transmitter cpu interrupt requests. 12.3.9 receiver figure 12-6 shows the structure of the sci receiver. 12.3.10 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 12.3.11 character reception during an sci reception, the receive shift register shifts char acters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to th e scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie (scc2), is also set, the scrf bit generates a receiver cpu interrupt request.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 163 figure 12-6. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rxd internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 cgmxclk
data sheet mc68hc08as32 ? rev. 4.1 164 freescale semiconductor 12.3.12 data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a fr equency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchr onized at the following times (see figure 12-7 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) see page 170. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 172. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 174. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 175. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 178. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 179. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 179. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 r= reserved table 12-1. sci receiver i/o register summary
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 165 figure 12-7. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 12-2 summarizes the results of the start bit verification samples. if start bit verification is no t successful, the rt clock is reset and a new search for a start bit begins. rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd table 12-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0
data sheet mc68hc08as32 ? rev. 4.1 166 freescale semiconductor to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-3 summarizes the results of the data bit samples. note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-4 summarizes the results of the stop bit samples. table 12-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 12-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 167 12.3.13 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit (scs1) is set. a break character that has no stop bit also sets the fe bit. 12.3.14 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu (scc2), puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of tw o conditions on the pte1/rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiv er begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the pte1/r xd pin has been idle may cause the receiver to wake up immediately. 12.4 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a char acter to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie (scc2), enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in sc s1 indicates that 10 or 11 consecutive logic 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bit, ilie (scc2), enables the idle bit to generate cpu interrupt requests.
data sheet mc68hc08as32 ? rev. 4.1 168 freescale semiconductor 12.4.1 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie (scc3), enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie (scc3), enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie (scc3), enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie (scc3), enables pe to generate sci error cpu interrupt requests. 12.5 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 12.5.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not ac cessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not requir ed during wait mode, reduce power consumption by disabling the module bef ore executing the wait instruction. 12.5.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. 12.6 sci during bre ak module interrupts the system integration module (sim) contro ls whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 169 to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the br eak state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 12.7 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ? transmit data pte1/rxd ? receive data 12.7.1 pte0/txd (transmit data) the pte0/txd pin is the serial data out put from the sci transmitter. the sci shares the pte0/txd pin with port e. whe n the sci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). 12.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 12.8 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr)
data sheet mc68hc08as32 ? rev. 4.1 170 freescale semiconductor 12.8.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, incl uding idle, break, start, and stop bits. address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 12-8. sci control register 1 (scc1)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 171 m ? mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 12-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bi t position of a received character or an idle condition on the pt e1/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, t hen a string of logic 1s preceding the stop bit can cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. (see table 12-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 12-4 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 12-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 12-5. character format selection control bits character format m pen:pty start bits data bits pa rity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits
data sheet mc68hc08as32 ? rev. 4.1 172 freescale semiconductor 12.8.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt requests 0 = scte not enabled to generate cpu interrupt requests tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt requests 0 = scrf not enabled to generate cpu interrupt requests ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the tr ansmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pte0/txd pin. if software address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 12-9. sci control register 2 (scc2)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 173 clears the te bit, the transmitter completes any transmission in progress before the pte0/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle c haracter to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines w hether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the br eak character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logi c 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters transmitted note: do not toggle the sbk bit immediately after setting the scte bit because toggling sbk too early causes the sci to send a br eak character instead of a preamble. 12.8.3 sci control register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts
data sheet mc68hc08as32 ? rev. 4.1 174 freescale semiconductor r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see figure 12-11 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: r reset:uu000000 r = reserved u = unaffected figure 12-10. sci control register 3 (scc3)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 175 12.8.4 sci status register 1 sci status register 1 contains flags to signal the following conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set w hen the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register note: setting the te bit for the first time also sets the scte bit. setting the te and sctie bits generates an sci transmitter cpu request. tc ? transmission complete bit this read-only bit is set when the scte bit is set and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break character is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break character and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write:rrrrrrrr reset:11000000 r= reserved figure 12-11. sci status register 1 (scs1)
data sheet mc68hc08as32 ? rev. 4.1 176 freescale semiconductor interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 also is set and the dmare bit in scc3 is clear. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 12-12 shows the normal flag-clearing sequence and an example of an overr un caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-cl earing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 177 fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected figure 12-12. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
data sheet mc68hc08as32 ? rev. 4.1 178 freescale semiconductor 12.8.5 sci status register 2 sci status register 2 contains flags to signal two conditions: 1. break character detected 2. incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the pte1/rxd pin foll owed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiv er detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits, usually from noise or a baud rate mismatch or when the receiver det ects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read: rrrrrr bkf rpf write: r r reset:00000000 r= reserved figure 12-13. sci status register 2 (scs2)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 179 12.8.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading address $0018 accesses the r ead-only received data bits, r7?r0. writing to address $0018 writes the data to be transmitted, t7?t0. reset has no effect on the sci data register. 12.8.7 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 12-6 . reset clears scp1 and scp0. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 12-14. sci data register (scdr) address: $0019 bit 7654321bit 0 read: r r scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 r= reserved figure 12-15. sci baud rate register (scbr) table 12-6. sci baud rate prescaling scp1:scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13
data sheet mc68hc08as32 ? rev. 4.1 180 freescale semiconductor scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 12-7 . reset clears scr2:scr0. use the following formula to calculate the sci baud rate: pd = prescale divisor (see table 12-6 ) bd = baud rate divisor (see table 12-7 ) table 12-8 shows the sci baud rates that can be generated with a 4.194-mhz crystal. table 12-7. sci baud rate selection scr2:scr1:scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate cgmxclk 64 pd bd ------------------------------------ =
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 181 table 12-8. sci baud rate selection examples scp1:scp0 prescaler divisor (pd) scr2:scr1:scr0 baud rate divisor (bd) baud rate (f xclk = 4.194 mhz) 00 1 000 1 65,531 00 1 001 2 32,766 00 1 010 4 16,383 00 1 011 8 8191 00 1 100 16 4095 00 1 101 32 2048 00 1 110 64 1024 00 1 111 128 512 01 3 000 1 21,844 01 3 001 2 10,922 01 3 010 4 5461 01 3 011 8 2730 01 3 100 16 1365 01 3 101 32 683 01 3 110 64 341 01 3 111 128 171 10 4 000 1 16,383 10 4 001 2 8191 10 4 010 4 4096 10 4 011 8 2048 10 4 100 16 1024 10 4 101 32 512 10 4 110 64 256 10 4 111 128 128 11 13 000 1 5041 11 13 001 2 1664 11 13 010 4 1260 11 13 011 8 630 11 13 100 16 315 11 13 101 32 158 11 13 110 64 78.8 11 13 111 128 39.4
data sheet mc68hc08as32 ? rev. 4.1 182 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 183 data sheet ? mc68hc08as32 section 13. system inte gration module (sim) 13.1 introduction this section describes the system integr ation module (sim), which supports up to 24 external and/or internal interrupts. the sim is a system state controller that coordinates cpu and excepti on timing. together with t he central processor unit (cpu), the sim controls all mcu activities. a block diagram of the sim is shown in figure 13-2 . figure 13-3 is a summary of the sim input/output (i/o) registers. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources
data sheet mc68hc08as32 ? rev. 4.1 184 freescale semiconductor figure 13-1. block diagram highlighting sim block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 185 figure 13-2. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop from cpu cpu wait from cpu simoscen to cgm cgmout from cgm internal clocks master reset control reset pin logic lvi from lvi module illegal opcode from cpu illegal address from address map decoders cop from cop module interrupt sources cpu interface reset control sim counter cop clock cgmxclk from cgm 2 addr. register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 198. read: rrrrrr sbsw r write: reset: 0 $fe01 sim reset status register (srsr) see page 199. read: por pin cop ilop ilad 0 lvi 0 write:rrrrrrrr reset:10000000 $fe03 sim break flag control register (sbfcr) see page 199. read: por pin cop ilop ilad 0 lvi 0 write:rrrrrrrr reset:10000000 r=reserved figure 13-3. sim i/o register summary
data sheet mc68hc08as32 ? rev. 4.1 186 freescale semiconductor table 13-1 shows the internal signal names used in this section. 13.2 sim bus clock co ntrol and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are gener ated from an incoming clock, cgmout, as shown in figure 13-4 . this clock can come from either an external oscillator or from the on-chip pll. (see section 5. clock generator module (cgm) .) 13.2.1 bus timing in user mode , the internal bus frequency is eith er the crystal oscillator output (cgmxclk) divided by four or the pll ou tput (cgmvclk) divided by four. (see section 5. clock generator module (cgm) .) 13.2.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after 4096 cgmxclk cycles. the rst pin is driven low by the sim during this entire period. the bus clocks start upon completion of the timeout. table 13-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 187 figure 13-4. cgm clock signals 13.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 13.6.2 stop mode .) in wait mode, the cpu clocks are i nactive. however, some modules can be programmed to be active in wait mode. re fer to the wait mode subsection of each module to see if the m odule is active or inactive in wait mode. 13.3 reset and syst em initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address each of these resets produces the vector $fffe?ffff ($fefe?feff in monitor mode) and asserts the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 13.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 13.7 sim registers .) pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode
data sheet mc68hc08as32 ? rev. 4.1 188 freescale semiconductor 13.3.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 13-2 for details. figure 13-5 shows the relative timing. figure 13-5. external reset timing 13.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. t he internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 13-6 ). an internal reset can be caused by an illegal address, illega l opcode, cop timeout, lvi, or por (see figure 13-7 . note: for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal re set signal then follows the sequence from the falling edge of rst shown in figure 13-6 . figure 13-6. internal reset timing table 13-2. pin bit set timing reset type number of cycl es required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 189 figure 13-7. sources of internal reset the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 13.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. another 64 cgmxclk cycles later, t he cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are held inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. see figure 13-8 . 13.3.2.2 computer operating properly (cop) reset the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr) if the copd bit in the mor register is at logic 0. (see section 6. computer operating properly (cop) .) illegal address rst illegal opcode rst coprst lvi por internal reset
data sheet mc68hc08as32 ? rev. 4.1 190 freescale semiconductor figure 13-8. por recovery 13.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. note: a $9e opcode (pre-byte for sp instru ctions) followed by an $8e opcode (stop instruction) generates a stop mode recovery reset. if the stop enable bit, stop, in the mor regist er is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. 13.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 13.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit (lvi) module asserts its output to the sim when the v dd voltage falls to the v lvif voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwr and lvirst bits in the config register are at logic 1. the rst pin will be held low until the sim counts 4096 cgmxclk cycles after v dd rises above v lvir . another 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. (see section 9. low-voltage inhibit (lvi) .) porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 191 13.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bi ts long and is clock ed by the falling edge of cgmxclk. 13.4.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. 13.4.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mor register. if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long start up times from stop mode. external crystal applications should use the full stop recovery time with ssrec cleared. 13.4.3 sim counter and reset states external reset has no effect on the sim counter. (see 13.6.2 stop mode for details.) the sim counter is free-running after all reset states. (see 13.3.2 active resets from internal sources for counter control and internal reset recovery sequences.) 13.5 program e xception control normal, sequential program execution can be changed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts
data sheet mc68hc08as32 ? rev. 4.1 192 freescale semiconductor 13.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 13-9 shows interrupt entry timing. figure 13-10 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. (see figure 13-11 .) figure 13-9. hardware interrupt entry figure 13-10. hardware interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [15:8] pc ? 1 [7: 0] opcode operand i bit
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 193 figure 13-11. interrupt processing no no no yes no no yes no yes yes as many interrupts i bit set? from reset break interrupt? i bit set? irq0 interrupt? irq1 interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip
data sheet mc68hc08as32 ? rev. 4.1 194 freescale semiconductor 13.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the si m checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 13-12 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m68hc05, m6805, and m146805 families, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or us es the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. figure 13-12 . interrupt recognition example 13.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 195 13.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 13.5.3 break interrupts the break module can stop normal prog ram flow at a software-programmable break point by asserting its break interrupt output. (see section 16. development support .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how the break state affects each module. 13.5.4 status flag protection in break mode the sim controls whether status flags co ntained in other modules can be cleared during break mode. the user can select to protect flags from being cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). (see 13.7.3 sim break flag control register .) protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as usual. 13.6 low-power modes executing the wait or stop instruction puts the mcu in a low-power mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 13.6.1 wait mode in wait mode, the cpu clocks are inacti ve while one set of peripheral clocks continues to run. figure 13-13 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode.
data sheet mc68hc08as32 ? rev. 4.1 196 freescale semiconductor wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw , in the sim break status register (sbsr). if the cop disable bit, copd, in th e mask option regist er (mor $001f) is logic 0, then the computer operati ng properly module (cop) is enabled and remains active in wait mode. figure 13-13. wait mode entry timing figure 13-14 and figure 13-15 show the timing for wait recovery. figure 13-14. wait recovery from interrupt or break figure 13-15. wait recovery from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 197 13.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripheral s. stop recovery time is selectable using the short stop recovery (ssrec) bit in the mor register ($001f). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applicat ions using canned oscill ators that do not require long startup times from stop mode. note: external crystal applications should use t he full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 13-16 shows stop mode entry timing and figure 13-17 shows the recovery from interrupt or break timing. figure 13-16. stop mode entry timing figure 13-17. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
data sheet mc68hc08as32 ? rev. 4.1 198 freescale semiconductor 13.7 sim registers the sim has three memory mapped registers. 13.7.1 sim break status register the sim break status register contains a flag to indicate that a break caused an exit from stop mode or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait mode or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode exited by break interrupt 0 = stop mode or wait mode not exited by break interrupt sbsw can be read within the break state sw i routine. the user can modify the return address on the stack by subtracti ng one from it. the following code is an example of this. writing 0 to the sbsw bit clears it. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: reset: 0 r= reserved figure 13-18. sim break status register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 199 13.7.2 sim reset status register this register contains six flags that show the source of the last reset. the status register will clear automatically after reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write:rrrrrrrr reset:10000000 r= reserved figure 13-19. sim reset status register (srsr)
data sheet mc68hc08as32 ? rev. 4.1 200 freescale semiconductor 13.7.3 sim break flag control register the sim break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit in some module registers, this read/writ e bit will enable software to clear status bits by accessing status registers only while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set.this operation is important for modules with status bits which can be cleared only by being read. see the register descriptions in each module for additional details. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 13-20. sim break flag control register (sbfcr)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 201 data sheet ? mc68hc08as32 section 14. serial peri pheral interface (spi) 14.1 introduction this section describes the serial peripheral interface (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 14.2 features features of the spi module include: full-duplex operation master mode and slave mode double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts with cpu service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility
data sheet mc68hc08as32 ? rev. 4.1 202 freescale semiconductor figure 14-1. block diagram highlighting spi block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 203 14.3 pin name and regi ster name conventions the generic names of the spi input/output (i/o) pins are: ss (slave select) spsck (spi serial clock) mosi (master out/slave in) miso (master in/slave out) the spi shares four i/o pins with a parallel i/o port. the full name of an spi pin reflects the name of the shared port pin. table 14-1 shows the full names of the spi i/o pins. the generic pin names appear in the text that follows. the generic names of the spi i/o registers are: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) table 14-2 shows the names and the addresses of the spi i/o registers. table 14-1. pin name conventions spi generic pin name: miso mosi ss spsck full spi pin name: pte5/miso pte6/mosi pte4/ss pte7/spsck table 14-2. i/o register addresses register name address spi control register $0010 spi status and control register $0011 spi data register $0012
data sheet mc68hc08as32 ? rev. 4.1 204 freescale semiconductor 14.4 functional description figure 14-3 summarizes the spi i/o registers and figure 14-2 shows the structure of the spi module. the spi module allows full-duplex, sy nchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. all spi interrupts can be serviced by the cpu. the following paragraphs describe the operation of the spi module. figure 14-2. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus bus clock modfen errie control modf spmstr mosi miso spsck ss
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 205 14.4.1 master mode the spi operates in master mode when the spi master bit, spmstr (spcr $0010), is set. note: configure the spi modules as master and slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. (see 14.13.1 spi control register .) only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte (spsc r $0011). the byte be gins shifting out on the mosi pin under the control of the serial clock. (see figure 14-4 .) figure 14-4. full-duplex master-slave connections addr. register name bit 7 6 5 4 3 2 1 bit 0 $0010 spi control register (spcr) see page 221. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0011 spi status and control register (spscr) see page 223. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0012 spi data register (spdr) see page 225. read:r7r6r5 r4 r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r= reserved figure 14-3. spi i/o register summary shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
data sheet mc68hc08as32 ? rev. 4.1 206 freescale semiconductor the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 14.13.2 spi status and control register .) through the spsck pin, the baud rate generator of the mast er also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf (spscr), becomes set. at the same ti me that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register and then reading the spi data register. writing to the spi data register clears the spte bit. 14.4.2 slave mode the spi operates in slave mode when the spmstr bit (spcr $0010) is clear. in slave mode the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be at logic 0. ss must remain low until the transmission is complete. (see 14.6.2 mode fault error .) in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it is transferred to the receive data register, and the sprf bit (spscr) is set. to prevent an overflow condition, slave software then must read the spi data register before another byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed, which is twice as fast as the fastest master spsck clock that can be generated. the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the sl ave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at leas t one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the sl ave shift register during a a transmission remains in a buffer until the end of the transmission.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 207 when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 14.5 transmission formats .) if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. note: to prevent spsck from appearing as a cl ock edge, spsck must be in the proper idle state before the slave is enabled. 14.5 transmission formats during an spi transmission, data is simu ltaneously transmitted (shifted out serially) and received (shifted in serially). a se rial clock line synchronizes shifting and sampling on the two serial data lines. a slav e select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, t he slave select line can be used optionally to indicate a multiple-master bus contention. 14.5.1 clock phase and polarity controls software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spi contro l register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (cpha) control bit (sp cr) selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transm issions to allow a master device to communicate with peripheral slav es having different requirements. note: before writing to the cpol bit or the cpha bit (spcr), disable the spi by clearing the spi enable bit (spe). 14.5.2 transmission format when cpha = 0 figure 14-5 shows an spi transmission in wh ich cpha (spcr) is logic 0. the figure should not be used as a repl acement for data sheet parametric information.two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or sl ave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be
data sheet mc68hc08as32 ? rev. 4.1 208 freescale semiconductor reconfigured as general-purpose i/o not affecting the spi. (see 14.6.2 mode fault error .) when cpha = 0, the first spsck e dge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low again between each byte transmitted as shown in figure 14-6 . figure 14-5. transmission format (cpha = 0) figure 14-6. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmi t data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol = 1 mosi from master miso from slave ss to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 209 14.5.3 transmission format when cpha = 1 figure 14-7 shows an spi transmission in wh ich cpha (spcr) is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a mast er or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the ma ster and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 14.6.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsc k edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the tr ansmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift regist er after the current transmission. figure 14-7. transmission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol =1 mosi from master miso from slave ss to slave capture strobe
data sheet mc68hc08as32 ? rev. 4.1 210 freescale semiconductor 14.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), transmissions are started by a software write to the spdr ($0012). cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = 0, the sck signal remains inactive for the first half of the first sck cycle. when cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive to its ac tive level. the spi clock rate (selected by spr1?spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 14-8 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. it is only enabled when both the spe and spmstr bits (spcr) are set to conserve power. sck edges occur halfway through the low time of the internal mcu clock. since the spi cl ock is free-running, it is uncertain where the write to the spdr will occu r relative to the slower sck. this uncertainty causes the variation in the initiation delay shown in figure 14-8 . this delay will be no longer than a single spi bit time. that is, the maximum delay between the write to spdr and the start of the spi transmission is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. 14.6 error conditions two flags signal spi error conditions: 1. overflow (ovrfin spscr) ? failing to read the spi data register before the next byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. 2. mode fault error (modf in spscr) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 14.6.1 overflow error the overflow flag (ovrf in spscr) becomes set if the spi receive data register still has unread data from a previous trans mission when the capture strobe of bit 1 of the next transmission occurs. (see figure 14-5 and figure 14-7 .) if an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. theref ore, an overflow error always indicates the loss of data.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 211 figure 14-8. transmission start delay (master) ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. modf and ovrf can gener ate a receiver/error cpu interrupt request. (see figure 14-11 .) it is not possibl e to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without over flow interrupts enabled causes the mcu write to spdr initiation delay bus mosi sck cpha = 1 sck cpha = 0 sck cycle number msb bit 6 12 clock write to spdr earliest latest sck = internal clock 2; earliest latest 2 possible start points sck = internal clock 8; 8 possible start points earliest latest sck = internal clock 32; 32 possible start points earliest latest sck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? initiation delay from write spdr to transfer begin
data sheet mc68hc08as32 ? rev. 4.1 212 freescale semiconductor to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 14-9 shows how it is possi ble to miss an overflow. figure 14-9. missed read of overflow condition the first part of figure 14-9 shows how to read the spscr and spdr to clear the sprf without problems. however, as ill ustrated by the second transmission example, the ovrf flag can be set in between the time that spscr and spdr are read. in this case, an overflow can be easily missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr a fter the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will comple te with an sprf interrupt. figure 14-10 illustrates this process. generally, to avoid this sec ond spscr read, enable the ovrf to the cpu by setting the errie bit (spscr). read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is set. byte 4 is lost. and ovrf bit clear. and ovrf bit clear.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 213 figure 14-10. clearing sprf when ovrf interrupt is not enabled 14.6.2 mode fault error for the modf flag (in spscr) to be set, the mode fault error enable bit (modfen in spscr) must be set. clearing the mo dfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 14-11 .) it is not possibl e to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear.
data sheet mc68hc08as32 ? rev. 4.1 214 freescale semiconductor note: to prevent bus contention with another master spi after a mode fault error, clear all data direction register (ddr) bits associated with the spi shared port pins. setting the modf flag (spscr) does not clear the spmstr bit. reading spmstr when modf = 1 will indicate that a mode fault error occurred in either master mode or slave mode. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck returns to its idle level after the shift of the eighth data bit. when cpha = 1, the tran smission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level after t he shift of the last data bit. (see 14.5 transmission formats .) note: when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if a transmission has begun. to clear the modf flag, read the spscr and then write to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag will not be cleared. 14.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests, as shown in table 14-3 . table 14-3. spi interrupts flag request spte (transmitter empty) spi transmitter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (overflow) spi receiver/e rror interrupt request (errie = 1) modf (mode fault) spi receiver/error in terrupt request (errie = 1, modfen = 1)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 215 the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enabl es both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. figure 14-11. spi interrupt request generation two sources in the spi status and control register can generate cpu interrupt requests: 1. spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate an spi receiver/error cpu interrupt request. 2. spi transmitter empty (spte) ? t he spte bit becomes set every time a byte transfers from the transmit data re gister to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. 14.8 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmiss ion has completed. the spi transmitter empty flag (spte in spscr) indicates w hen the transmit data buffer is ready to accept new data. write to the spi data re gister only when the spte bit is high. figure 14-12 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha?cpol = 1?0). spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request
data sheet mc68hc08as32 ? rev. 4.1 216 freescale semiconductor figure 14-12. sprf/spte cpu interrupt timing the transmit data buffer allows back-to-b ack transmissions without the slave precisely timing its writes between transmis sions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the nex t data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus c ycles after the transmit buffer empties into the shift register. this allows the us er to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. bit 3 mosi spsck (cpha:cpol = 1:0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 217 14.9 resetting the spi any system reset completely resets the sp i. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaul ted back to being general-purpose i/o. these additional items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regi ster (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to reset all c ontrol bits when spe is set back to high for the next transmission. by not resetting the sprf, ovrf, and modf fl ags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi also can be disabl ed by a mode fault occurring in an spi that was configured as a master with the modfen bit set. 14.10 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 14.10.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not ac cessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not requi red during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow c ondition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 14.7 interrupts .)
data sheet mc68hc08as32 ? rev. 4.1 218 freescale semiconductor 14.10.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after the mcu exits stop mode. if stop mode is exit ed by reset, any transfer in progress is aborted and the spi is reset. 14.11 spi during break interrupts the system integration module (sim) contro ls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr, $fe03) enables software to clear status bits during the break state. (see 13.7.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the br eak state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode w ill not initiate a transmission nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 14.12 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select v ss ? clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd .
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 219 14.12.1 miso (master in/slave out) miso is one of the two spi module pins t hat transmit serial data. in full duplex operation, the miso pin of the master sp i module is connected to the miso pin of the slave spi module. the master spi si multaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enab led only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direct ion of the miso pin regardless of the state of the data direction register of the shared i/o port. 14.12.2 mosi (master out/slave in) mosi is one of the two spi module pins t hat transmit serial data. in full duplex operation, the mosi pin of the master sp i module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direct ion of the mosi pin regardless of the state of the data direction register of the shared i/o port. 14.12.3 spsck (serial clock) the serial clock synchronizes data tr ansmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full-duplex oper ation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 14.12.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 14.5 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low throughout the transmission for the cpha = 1 format. see figure 14-13 .
data sheet mc68hc08as32 ? rev. 4.1 220 freescale semiconductor figure 14-13. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 14.13.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignor es all incoming spsck clocks, even if a transmission already has begun. when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. (see 14.6.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shar ed i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. (see table 14-4 .) 14.12.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize radio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 table 14-4. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input only to spi x = don?t care
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 221 14.13 i/o registers three registers control and monitor spi operation: spi control register (spcr, $0010) spi status and control register (spscr, $0011) spi data register (spdr, $0012) 14.13.1 spi control register the spi control register: enables spi module interrupt requests selects cpu interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. (see figure 14-5 and figure 14-7 .) to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. address:$0010654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 14-14. spi control register (spcr)
data sheet mc68hc08as32 ? rev. 4.1 222 freescale semiconductor cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 14-5 and figure 14-7 .) to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 14-13 .) reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first ed ge of the spsck indica tes the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. (see 14.6.2 mode fault error .) a logic 1 on the ss pin does not in any way affect the state of the spi state machine. spwom ? spi wired-or mode bit this read/write bit disables the pull up devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins spe ? spi enable bit this read/write bit enables the spi modul e. clearing spe causes a partial reset of the spi. (see 14.9 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 223 14.13.2 spi status and control register the spi status and control register contai ns flags to signal th e following conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also co ntains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit, and reset also clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write:r rrr reset:00001000 r= reserved figure 14-15. spi status and control register (spscr)
data sheet mc68hc08as32 ? rev. 4.1 224 freescale semiconductor ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the rece ive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, ready-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi control register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since the transmit buffer empties into the shift register. this allo ws the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this im plies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does no t clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. (see 14.12.4 ss (slave select) .) if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 14.6.2 mode fault error .)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 225 spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 14-5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm), see section 5. clock generator module (cgm) . bd = baud rate divisor 14.13.3 spi data register the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data r egister reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. see figure 14-2 . r7?r0/t7?t0 ? receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the buffer read is not the same as the buffer written. table 14-5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-16. spi data register (spdr)
data sheet mc68hc08as32 ? rev. 4.1 226 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 227 data sheet ? mc68hc08as32 section 15. timer interface (tim) 15.1 introduction this section describes the timer interface module (tim6). the tim is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 15-2 is a block diagram of the tim. 15.2 features features of the tim include: six input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection ? external tim clock input (4-mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 15.3 functional description figure 15-2 shows the tim structure. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides t he timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh?tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time wi thout affecting the counting sequence. the six tim channels are programmable i ndependently as input capture or output compare channels.
data sheet mc68hc08as32 ? rev. 4.1 228 freescale semiconductor figure 15-1. block diagram highlighting tim block and pins break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 69 bytes user rom ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 224 bytes user rom vector space ? 36 bytes irq module ddrd ptd ddre pte internal bus osc1 osc2 cgmxfc rst irq v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13?ptd0/atd8 pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5 ptf2/tch4 ptf ddrf bdtxd bdrxd power ptf1/tch3 ptf0/tch2 byte data link controller digital module ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc4?ptc3 ptc2/mclk ptc1?ptc0 v refh user eeprom ? 512 bytes
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 229 figure 15-2. tim block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h?tch0l ms0a els0b els0a pte2 tof toie inter- channel 0 tmodh?tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd6/atd14/tclk pte2/tch0 pte3/tch1 ptf0/tch2 ptf1/tch3 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h?tch1l ms1a els1b els1a pte3 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h?tch2l ms2a els2b els2a ptf0 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h?tch3l ms3a els3b els3a ptf1 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic 16-bit comparator 16-bit latch tch4h?tch4l ms4a els4b els4a ptf2 channel 4 tov4 ch4ie ch4f ch5max ms4b logic inter- rupt logic 16-bit comparator 16-bit latch tch5h?tch5l ms5a els5b els5a ptf3 channel 5 tov5 ch5ie ch5f ch5max logic inter- rupt logic ptf2/tch4 ptf3/tch5
data sheet mc68hc08as32 ? rev. 4.1 230 freescale semiconductor addr. register name bit 7 6 5 4 3 2 1 bit 0 $0020 timer status and control register (tsc) see page 241. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0022 timer counter register high (tcnth) see page 242. read: bit 15 14 13 12 11 10 9 bit 8 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0023 timer counter register low (tcntl) see page 242. read: bit 7 6 5 4 3 2 1 bit 0 write:rrr r rrrr reset: 0 0 0 0 0 0 0 0 $0024 timer modulo register high (tmodh) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0025 timer modulo register low (tmodl) see page 243. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0026 timer channel 0 status and control register (tsc0) see page 244. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0027 timer channel 0 register high (tch0h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 timer channel 0 register low (tch0l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0029 timer channel 1 status and control register (tsc1) see page 244. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $002a timer channel 1 register high (tch1h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b timer channel 1 register low (tch1l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002c timer channel 2 status and control register (tsc2) see page 244. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 r = reserved figure 15-3. tim i/o register summary (sheet 1 of 2)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 231 $002d timer channel 2 register high (tch2h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer channel 2 register low (tch2l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002f timer channel 3 status and control register (tsc3) see page 244. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $0030 timer channel 3 register high (tch3h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer channel 3 register low (tch3l see page 248. ) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0032 timer channel 4 status and control register (tsc4) see page 244. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 0 0 0 0 0 0 0 0 $0033 timer channel 4 register high (tch4h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 timer channel 4 register low (tch4l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0035 timer channel 5 status and control register (tsc5) see page 244. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset: 0 0 0 0 0 0 0 0 $0036 timer channel 5 register high (tch5h) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer channel 5 register low (tch5l) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved figure 15-3. tim i/o register summary (sheet 2 of 2)
data sheet mc68hc08as32 ? rev. 4.1 232 freescale semiconductor 15.3.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, ptd6/atd14/tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2?0], in the tim status and control register select the tim clock source. 15.3.2 input capture an input capture function has three basi c parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the polarity of the active edge is programmabl e. the level transition which triggers the counter transfer is defined by the co rresponding input edge bits (elsxb and elsxa in tsc0 through tsc5 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh?tchxl. input captures can generate tim cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. the free-running counter contents are transferred to the tim channel registers (tchxh?tchxl) (see 15.8.5 tim channel registers ) on each proper signal transition regardless of whether the tim channel flag (ch0f?ch5f in tsc0?tsc5 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register when the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case, an input capture function is used in conjunction with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 15.8.5 tim channel registers ). because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 233 reset does not affect the contents of the input capture channel (tchxh?tchxl) registers. 15.3.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 15.3.3.1 unbuffere d output compare any output compare channel can generate unbuffered output compare pulses as described in 15.3.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim ch annel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchroni ze unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the output.
data sheet mc68hc08as32 ? rev. 4.1 234 freescale semiconductor setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the pte2/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 register s to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the output. setting the ms2b bit in tim channel 2 stat us and control register (tsc2) links channel 2 and channel 3. the output compare value in the tim channel 2 registers initially controls the output on the ptf0/tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 register s to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (2 or 3) that control the output are the ones written to last. tsc2 controls and monitors the buffered output compare function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the output. setting the ms4b bit in tim channel 4 stat us and control register (tsc4) links channel 4 and channel 5. the output compare value in the tim channel 4 registers initially controls the output on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5 register s to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (4 or 5) that control the output are the ones written to last. tsc4 controls and monitors the buffered output compare function, and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new val ue to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 15.3.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm si gnal. the channel pin toggles when the
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 235 counter reaches the value in the tim count er modulo registers. the time between overflows is the period of the pwm signal. as figure 15-4 shows, the output compare value in the tim channel registers determines the pulse width of the pw m signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. figure 15-4. pwm period and pulse width the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 15.8.1 tim status and control register ). the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 15.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 15.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing t he new pulse width value over the value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter re aches the old value but after the counter reaches the new value prevents any compar e during that pwm period. also, using a tim overflow interrupt routine to wr ite a new, smaller pulse width value may ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare
data sheet mc68hc08as32 ? rev. 4.1 236 freescale semiconductor cause the compare to be missed. the ti m may pass the new value before it is written to the timer channel (tchxh/tchxl) registers. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse wi dth, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 15.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte2/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tim channel 2 stat us and control register (tsc2) links channel 2 and channel 3. the tim channel 2 registers initially control the pulse width on the ptf0/tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 controls and monitors the buffered pwm function, and tim channel 3 status and control register
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 237 (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered pwm channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms4b bit in tim channel 4 stat us and control register (tsc4) links channel 4 and channel 5. the tim channel 4 registers initially control the pulse width on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (4 or 5) that control the pulse width are the ones written to last. tsc4 controls and monitors the buffered pwm function, and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write pulse width values to the currently active channel registers. user software s hould track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 15.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh?tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh?tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0?1 (for unbuffered output compare or pwm signals) or 1?0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa. (see table 15-2 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1?0 (to clear output on compare) or 1?1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 15-2 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation
data sheet mc68hc08as32 ? rev. 4.1 238 freescale semiconductor and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h?tch0l) initially control the buffered pwm output. tim status control register 0 (tsc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim channel 2 registers (tch2h?tch2l) initially control the buffered pwm output. tim status control register 2 (tsc2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. setting ms4b links channels 4 and 5 and configures them for buffered pwm operation. the tim channel 4 registers (tch4h?tch4l) initially control the buffered pwm output. tim status control register 4 (tsc4) controls and monitors the pwm signal from the linked channels. ms4b takes priority over ms4a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 15.8.4 tim channel status and control registers .) 15.4 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enabl es tim overflow interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch5f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. 15.5 low-power modes the wait and stop instructions put the mcu in low-power standby modes.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 239 15.5.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 15.5.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode. 15.6 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) contro ls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 13.7.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 15.7 i/o signals port d shares one of its pins with the tim. port e shares two of its pins with the tim and port f shares four of its pins with the tim. ptd6/atd14/tclk is an external clock input to the tim prescaler. the si x tim channel i/o pins are pte2/tch0, pte3/tch1, ptf0/tch2, ptf1/tch3, ptf2/tch4, and ptf3/tch5. 15.7.1 tim clock pin (ptd6/atd14/tclk) ptd6/atd14/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the ptd6/atd14/tclk input by writing logic 1s to the three prescaler select bits,
data sheet mc68hc08as32 ? rev. 4.1 240 freescale semiconductor ps[2?0]. (see 15.8.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. ptd6/atd14/tclk is available as a general-purpose i/o pin or adc channel when not used as the tim clock input. when the ptd6/atd14/tclk pin is the tim clock input, it is an input regardless of t he state of the ddrd6 bit in data direction register d. 15.7.2 tim channel i/o pins (ptf3/t ch5?ptf0/tch2 and pte3/tch1?pte2/tch0) each channel i/o pin is programmable inde pendently as an input capture pin or an output compare pin. pte2/tch0, pte6/tch2, and ptf2/tch4 can be configured as buffered output compare or buffered pwm pins. 15.8 i/o registers these i/o registers control and monitor tim operation: tim status and control register (tsc) tim control registers (tcnth?tcntl) tim counter modulo registers (tmodh?tmodl) tim channel status and control registers (tsc0, tsc1, tsc2, tsc3, tsc4, and tsc5) tim channel registers (tch0h?tch0l, tch1h?tch1l, tch2h?tch2l, tch3h?tch3l, tch4h?tch4l, and tch5h?tch5l) 15.8.1 tim status and control register the tim status and control register: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock 1 bus frequency ------------------------------------- t su +
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 241 tof ? tim overflow flag bit this read/write flag is set when the tim counter resets reaches the modulo value programmed in the tim counter m odulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overfl ow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, sto pping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wa it mode if the tim is required to exit wait mode. also when the tstop bit is set and the timer is configured for input capture operation, input captures are in hibited until the tstop bit is cleared. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after t he tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneous ly stops the tim counter at a value of $0000. address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 15-5. tim status and control register (tsc)
data sheet mc68hc08as32 ? rev. 4.1 242 freescale semiconductor ps[2?0] ? prescaler select bits these read/write bits select either the ptd6/atd14/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 15-1 shows. reset clears the ps[2?0] bits. 15.8.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if tcnth is read during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 15-1. prescaler selection ps[2?0] tim clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 ptd6/atd14/tclk register name and address tcnth ? $0022 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address tcntl ? $0023 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 rr = reserved figure 15-6. tim counter registers (tcnth and tcntl)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 243 15.8.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. 15.8.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation register name and address tmodh ? $0024 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tmodl ? $0025 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 15-7. tim counter modulo registers (tmodh and tmodl)
data sheet mc68hc08as32 ? rev. 4.1 244 freescale semiconductor register name and address tsc0 ? $0026 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tsc1 ? $0029 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved register name and address tsc2 ? $002c bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 register name and address tsc3 ? $002f bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset:00000000 register name and address tsc4 ? $0032 bit 7654321bit 0 read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 register name and address tsc5 ? $0035 bit 7654321bit 0 read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset:00000000 rr = reserved figure 15-8. tim channel status and control registers (tsc0?tsc5)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 245 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pi n. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when chxie = 1, clear chxf by reading tim channel x status and control register with chxf set, and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0, tim channel 2, and tim channel 4 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3 pin to general-purpose i/o. setting ms4b disables the channel 5 status and control register and reverts tch5 pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb?elsxa 00, this read/write bit se lects either input capture operation or unbuffered output compare/pwm operation. (see table 15-2 .) 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb?elsxa = 00, this read/write bit selects the initial output level of the tchx pin once pwm, input capture, or output compare operation is enabled. (see table 15-2 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high
data sheet mc68hc08as32 ? rev. 4.1 246 freescale semiconductor note: before changing a channel function by wr iting to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e or port f, and pin ptex/tchx or pin ptfx /tchx is available as a general-purpose i/o pin. however, channel x is at a st ate determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 15-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: before enabling a tim channel register for input capture operation, make sure that the ptex/tchx pin or ptfx/tchx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggl e on tim counter overflow. table 15-2. mode, edge, and level selection msxb?msxa elsxb?elsxa mode configuration x0 00 output preset pin under port control; initialize timer output level high x1 00 pin under port control; initialize timer output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 247 note: when tovx is set, a tim counter overfl ow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 15-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100% duty cycle level until the cycle after chxmax is cleared. note: the pwm 0% duty cycle is defined as output low all of the time. to generate the 0% duty cycle, select clear output on compare and then clear the tovx bit (chxmax = 0). the pwm 100% duty cycle is defined as output high all of the time. to generate the 100% duty cycle, use the chxmax bit in the tscx register. figure 15-9. chxmax latency 15.8.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb?msxa = 0?0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb?msxa 0?0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
data sheet mc68hc08as32 ? rev. 4.1 248 freescale semiconductor register name and address tch0h ? $0027 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch0l ? $0028 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch1h ? $002a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch1l ? $002b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch2h ? $002d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch2l ? $002e bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch3h ? $0030 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset figure 15-10. tim channel registers (tch0h/l?tch3h/l) (sheet 1 of 2)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 249 register name and address tch3l ? $0031 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch4h ? $0033 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch4l ? $0034 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch5h ? $0036 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch5l ? $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 15-10. tim channel registers (tch0h/l?tch3h/l) (sheet 2 of 2)
data sheet mc68hc08as32 ? rev. 4.1 250 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 251 data sheet ? mc68hc08as32 section 16. development support 16.1 introduction this section describes the break module, the monitor read-only memory (mon), and the monitor mode entry methods. 16.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 16.2.1 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 16-1 shows the structure of the break module.
data sheet mc68hc08as32 ? rev. 4.1 252 freescale semiconductor figure 16-1. break module block diagram 16.2.1.1 flag protection during break interrupts the system integration module (sim) contro ls whether module status bits can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 13.7.3 sim break flag control register and the break interrupts subsection for each module.) iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt to sim addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe0c break address register high (brkh) see page 254. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $fe0d break address register low (brkl) see page 254. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $fe0e break status and control regis- ter (brkscr) see page 253. read: brke brka 000000 write: r r rrrr reset: 0 0 0 0 0 0 0 0 r = reserved figure 16-2. break i/o register summary
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 253 16.2.1.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc?$fffd ($fefc?$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 16.2.1.3 tim during break interrupts a break interrupt stops the timer counter. 16.2.1.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. for v hi , see 17.4 5.0-volt dc electrical characteristics . 16.2.2 break module registers three registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) 16.2.2.1 break status and control register the break status and control register contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: rrrrrr reset:00000000 r= reserved figure 16-3. break status and control register (brkscr)
data sheet mc68hc08as32 ? rev. 4.1 254 freescale semiconductor brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 16.2.2.2 break address registers the break address registers contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 16.2.3 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 16.2.3.1 wait mode if enabled, the break module is active in wait mode. the sim break stop/wait bit (sbsw) in the sim break status register indicates whether wait was exited by a break interrupt. if so, the user can modi fy the return address on the stack by subtracting one from it to re-execute the stop or wait opcode. (see 13.7.1 sim break status register .) 16.2.3.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. a break interru pt will cause an exit from stop mode and sets the sbsw bit in the sim break status register. address: $fe0c bit 7654321bit 0 read: bit 15 bit 13 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-4. break address register (brkh) address: $fe0d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-5. break address register (brkl)
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 255 16.3 monitor rom (mon) the monitor rom allows complete test ing of the mcu through a single-wire interface with a host computer. features of the monitor rom include: normal user-mode pin functionality one pin dedicated to serial communi cation between monitor rom and host computer standard mark/space non-return-to-ze ro (nrz) communication with host computer 4800 baud?28.8 kbaud communication with host computer execution of code in ram or rom 16.3.1 functional description monitor rom receives and executes commands from a host computer. figure 16-6 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the mc68hc08as32 has a rom security feature that requires proper procedures to be followed before the rom can be access ed. access to the rom is denied to unauthorized users of customer-specified software. in monitor mode, the mcu can execute hos t-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor.
data sheet mc68hc08as32 ? rev. 4.1 256 freescale semiconductor figure 16-6. monitor mode circuit + + + 10 m ? x1 v dd v dda v dd + v hi mc145407 mc74hc125 68hc08 rst irq1 /v pp v dda /v ddaref cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 0.1 f 10 ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc3 v dd 10 k ? b a note: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 + ptc0 ptc1 v dd 10 k ?
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 257 16.3.1.1 entering monitor mode table 16-1 shows the pin conditions for entering monitor mode. enter monitor mode by either: executing a software interrupt instruction (swi) or applying a logic 0 and then a logic 1 to the rst pin the mcu sends a break signal (10 consec utive logic 0s) to the host computer, indicating that it is ready to receive a command. the break si gnal also provides a timing reference to allow the host to determine the necessary baud rate. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor fi rmware instead of user code. the cop module is disabled in m onitor mode as long as v dd +v hi (see 17.4 5.0-volt dc electrical characteristics ) is applied to either the irq pin or the v dd pin. (see section 13. system integration module (sim) for more information on modes of operation.) note: holding the ptc3 pin low when enteri ng monitor mode causes a bypass of a divide-by-two stage at the oscillator . the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must ha ve a 50% duty cycle at maximum bus frequency. table 16-2 is a summary of the differences between user mode and monitor mode. table 16-1. mode selection irq pin ptco pin ptc1 pin pta0 pin ptc3 pin mode cgmout bus frequency v dd + v hi (1) 1011monitor or v dd + v hi (1) 1010monitor cgmxclk 1. for v hi , see 17.4 5.0-volt dc elect rical characteristics and 17.1 maximum ratings cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- table 16-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd 1. if the high voltage (v dd + v hi ) is removed from the irq /v pp pin while in monitor mode, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by t he copd bit in the configuration register. (see 17.4 5.0-volt dc electrical characteristics .)
data sheet mc68hc08as32 ? rev. 4.1 258 freescale semiconductor 16.3.1.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 16-7 and figure 16-8 .) the data transmit and receive rate can be anywhere from 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. figure 16-7. monitor data format figure 16-8. sample monitor waveforms 16.3.1.3 echoing as shown in figure 16-9 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 16-9. read transaction 16.3.1.4 break signal a start bit followed by nine low bits is a break signal. (see figure 16-10 .) when the monitor receives a break signal, it drives t he pta0 pin high for the duration of two bits before echoi ng the break signal. figure 16-10. break transaction bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 259 16.3.1.5 commands the monitor rom uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program a sequence of iread or iwrite comman ds can access a block of memory sequentially over the full 64-kbyte memory map. table 16-3. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 16-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data
data sheet mc68hc08as32 ? rev. 4.1 260 freescale semiconductor table 16-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result table 16-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor table 16-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 261 16.3.1.6 baud rate with a 4.9152-mhz crystal and the ptc3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 960 0. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7:4] bits in the pll programming register (ppg). (see section 5. clock generator module (cgm) .) table 16-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 16-9. monitor baud rate selection vco frequency multiplier (n) 123456 monitor baud rate (4.9152 mhz) 4800 9600 14,400 19,200 24,000 28,800 monitor baud rate (4.194 mhz) 4096 8192 12,288 16,384 20,480 24,576
data sheet mc68hc08as32 ? rev. 4.1 262 freescale semiconductor
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 263 data sheet ? mc68hc08as32 section 17. electrical specifications 17.1 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 17.4 5.0-volt dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any volta ge higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) rating (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma reset irq input voltage v hi v dd to v dd + 2 v
data sheet mc68hc08as32 ? rev. 4.1 264 freescale semiconductor 17.2 functional o perating range 17.3 thermal characteristics rating symbol value unit operating temperature range t a ?40 to 125 c operating voltage range v dd 5.0 10% v characteristic symbol value unit thermal resistance plcc (52 pins) ja 50 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined from a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + (p d 2 x ja ) w/ c average junction temperature t j t a = p d ja c maximum junction temperature t jm 150 c
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 265 17.4 5.0-volt dc elect rical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all ports, rst v oh v dd ?0.8 ?? v output low voltage (i load = 1.6 ma) all ports, rst v ol ??0.4v input high voltage all ports, irq s , reset, osc1 v ih 0.7 x v dd ? v dd v input low voltage all ports, irq s , reset, osc1 v il v ss ? 0.3 x v dd v v dd + v dda /v ddaref supply cur rent run (3) wait (4) stop (5) 25 c ?40 c to +105 c ?40 c to +125 c 25 c with lvi enabled ?40 c to +105 c with lvi enabled i dd ? ? ? ? ? ? ? ? ? ? ? ? 30 15 5 50 100 400 500 ma ma a a a a a i/o ports hi-z leakage current i l ?? 1 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf low-voltage reset inhibit v lv f 3.7 4.1 4.45 v low-voltage reset inhibit/recover hysteresis h lv i 50 150 ? mv por rearm voltage (6) v por 0 ? 200 mv por reset voltage (7) v porrst 0 ? 800 mv por rise time ramp rate (8) r por 0.02 ? ? v/ms high cop disable voltage (9) v hi v dd v dd + 2 v 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +105 c, unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitanc e linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 vdc from rail. no dc loads. less than 100 pf on all outputs, c l = 20 pf on osc2. all ports configured as i nputs. osc2 capacitance linearly affects wait i dd . measured with all modules enabled. 5. stop i dd measured with osc1 = v ss . 6. maximum is highest vo ltage that por is guaranteed. 7. maximum is highest vo ltage that por is possible. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 9. see 6.8 cop module during break interrupts .
data sheet mc68hc08as32 ? rev. 4.1 266 freescale semiconductor 17.5 control timing 17.6 adc characteristics characteristic (1) symbol min max unit bus operating frequency (4.5?5.5 v ? v dd only) f bus ?8.4mhz rst pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 ? t cyc irq interrupt pulse period t ilil (2) ? t cyc eeprom programming time per byte t eepgm 10 ? ms eeprom erasing time per byte t ebyte 10 ? ms eeprom erasing time per block t eblock 10 ? ms eeprom erasing time per bulk t ebulk 10 ? ms eeprom programming volt age discharge period t eefpv 100 ? s 16-bit timer (3) input capture pulse width (2) input capture period t th, t tl t tltl 2 (4) ? ? t cyc 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +105 c, unless otherwise noted. 2. refer to table 15-2. mode, edge , and level selection and supporting note. 3. the 2-bit timer prescaler is the limitin g factor in determining timer resolution. 4. the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execut e the capture in terrupt service routine plus 1 t cyc . characteristic min max unit comments resolution 8 8 bits absolute accuracy (v refl = 0 v, v dda = v refh = 5 v 10%) ?1 +1 lsb includes quantization conversion range (1) v refl v refh v v refl = v ssa power-up time 16 17 s conversion time period input leakage (2) (3) ports b and d ? 1 a conversion time 16 17 adc clock cycles includes sampling time monotonicity inherent within total error zero input reading 00 01 hex v in = v refl full-scale reading fe ff hex v in = v refh sample time (2) (3) 5 ? adc clock cycles input capacitance ? 8 pf not tested adc internal clock 500 k 1.048 m hz tested only at 1 mhz analog input voltage ?0.3 v dd + 0.3 v 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v dda /v ddaref = 5.0 vdc 10%, v ssa = 0 vdc, v refh = 5.0 vdc 10% 2. the external system error caus ed by input leakag e current is approximately equal to t he product of r sour ce and input curren t. 3. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 267 17.7 5.0-vdc 10% serial peripheral interface (spi) timing num (1) characteristic (2) symbol min max unit operating frequency (3) master slave f b us ( m ) f b us (s) f b us /128 dc f b us /2 f b us mhz 1 cycle time master slave t cyc (m) t cyc (s) 2 1 128 ? t cyc 2 enable lead time t lead 15 ? ns 3 enable lag time t lag 15 ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 100 50 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 100 50 ? ? ns 6 data setup time, inputs master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time, inputs master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (4) cpha = 0 cpha = 1 t a(cp0) t a(cp1) 0 0 40 20 ns 9 slave disable time, hold time to high-impedance state t dis ?25ns 10 enable edge lead time to data valid (5) master slave t ev(m) t ev(s) ? ? 10 40 ns 11 enable edge lead time to data invalid master slave t ei(m) t ei(s) 0 5 ? ? ns 12 data valid master (before capture edge) t v(m) 90 --- ns 13 data hold time (outputs) master (after capture edge) t ho(m) 100 --- ns 1. item numbers refer to dimensions in figure 17-1 and figure 17-2 . 2. all timing is shown with respect to 30% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. 3. f b us = the currently active bus frequency for the microcontroller. 4. time to data active from high-impedance state 5. with 100 pf on all spi pins
data sheet mc68hc08as32 ? rev. 4.1 268 freescale semiconductor figure 17-1. spi master timing note note: this first cloc k edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 13 12 13
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 269 figure 17-2. spi slave timing note: not defined but normally msb of character just received slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11
data sheet mc68hc08as32 ? rev. 4.1 270 freescale semiconductor 17.8 cgm oper ating conditions 17.9 cgm compone nt information characteristic symbol min typ max unit crystal reference frequency f xclk 1? 8mhz range nominal multiplier f nom ?4.9152 ? mhz vco center-of-range frequency (1) f vrs 4.9152 ? 32.8 mhz medium voltage vco center-of-range frequency 4.9152 ? 16.4 mhz vco frequency multiplier n 1 ? 15 ? vco center-of-range multiplier l 1 ? 15 ? vco operating frequency f vclk f vrsmin ? f vrsmax mhz 1. 5.0 v 10% v dd only characteristic symbol min typ max unit crystal (x1) frequency (mhz) (1) f xclk 14.9152 8mhz crystal load capacitance (2) c l ?? ? f crystal fixed capacitance (2) c 1 ? 2 c l ? f crystal tuning capacitance (2) c 2 ? 2 c l ? f feedback bias resistor r b ?1 ?m ? series resistor (3) r s 0?3.3k ? filter capacitor c f ? c fact (v dda /f xclk ) ? f bypass capacitor (4) c byp ?0.1 ? f 1. fundamental mode crystals only 2. consult crystal manufacturer?s data. 3. not required 4. c byp must provide low ac impedance from f = f xclk /100 to 100 f vclk , so series resistance must be considered.
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 271 17.10 cgm acquisition/lock time information description symbol min typ max unit filter capacitor multiply factor c fact ? 0.0154 ? f/sv acquisition mode time factor k acq ? 0.1135 ? v tracking mode time factor k trk ? 0.0174 ? v manual mode time to stable (1) t acq ??s manual stable to lock time (1) t al ??sec manual acquisition time t lock ? t acq + t al ?sec tracking mode entry frequency tolerance ? trk 0? 3.6% ? acquisition mode entry frequency tolerance ? acq 6.3% ? 7.2% ? lock entry frequency tolerance ? lock 0? 0.9% ? lock exit frequency tolerance ? unl 0.9% ? 1.8% ? reference cycles per acqu isition mode measurement n acq ? 32 ? cycles reference cycles per trac king mode measurement n trk ? 128 ? cycles automatic mode time to stable (1) t acq ?sec automatic stable to lock time (1) t al ?sec automatic lock time t lock ? t acq + t al ?sec pll jitter (2) f j 0? f crys 0.025% 2 p n/4 hz 1. if c f chosen correctly 2. deviation of average bus frequency over 2 ms, n = vco frequency multiplier 8v dda f xclk k acq ---------------------------------- - 4 v dda f xclk k trk --------------------------------- - n acq f xclk ------------- - 8v dda f xclk k acq ---------------------------------- - n trk f xclk ------------- - 4 v dda f xclk k trk --------------------------------- -
data sheet mc68hc08as32 ? rev. 4.1 272 freescale semiconductor 17.11 timer modul e characteristics 17.12 ram characteristics 17.13 eeprom characteristics 17.14 bdlc transmitte r vpw symbol timings characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic symbol min max unit ram data retention voltage v rdr 0.7 ? v characteristic value unit eeprom write/erase cycles @ 10 ms write time + 85 c 10,000 cycles eeprom data retention after 10,000 write/erase cycles 10 years characteristic (1), (2) number symbol min typ max unit passive logic 0 10 t tvp1 62 64 66 s passive logic 1 11 t tvp2 126 128 130 s active logic 0 12 t tva1 126 128 130 s active logic 1 13 t tva2 62 64 66 s start-of-frame (sof) 14 t tva3 198 200 202 s end-of-data (eod) 15 t tvp3 198 200 202 s end-of-frame (eof) 16 t tv4 278 280 282 s inter-frame separator (ifs) 17 t tv6 298 300 302 s 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. see figure 17-3 .
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 273 17.15 bdlc receiver vpw symbol timings figure 17-3. bdlc variable pulse width modulation (vpw) symbol timing characteristic (1), (2), (3) number symbol min typ max unit passive logic 0 10 t trvp1 34 64 96 s passive logic 1 11 t trvp2 96 128 163 s active logic 0 12 t trva1 96 128 163 s active logic 1 13 t trva2 34 64 96 s start-of-frame (sof) 14 t trva3 163 200 239 s end-of-data (eod) 15 t trvp3 163 200 239 s end-of-frame (eof) 16 t trv4 239 280 320 s break 18 t trv6 280 ? ? s 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. the receiver symbol timing boundaries are subject to an uncertainty of 1 t bdlc s due to sampling considerations. 3. see figure 17-3 . 13 11 10 12 16 14 sof 15 18 0 0 1 1 eod brk 0 eof
data sheet mc68hc08as32 ? rev. 4.1 274 freescale semiconductor 17.16 bdlc transmitter dc electrical characteristics 17.17 bdlc receiver dc electrical characteristics characteristic (1) symbol min max unit bdtxd output low voltage (ibdtxd = 1.6 ma) v oltx ?0.4 v bdtxd output high voltage (ibdtx = ?800 a) v ohtx v dd ?0.8 ?v 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted characteristic (1) symbol min max unit bdrxd input low voltage v ilrx v ss 0.3 x v dd v bdrxd input high voltage v ihrx 0.7 x v dd v dd v bdrxd input low current i ilbdrxi ?1 +1 a bdrxd input high current i hbdrx ?1 +1 a 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 275 data sheet ? mc68hc08as32 section 18. ordering informatio n and mechanical specifications 18.1 introduction this section provides ordering information for the mc68hc08as32 along with the dimensions for: 52-pin plastic leaded chip carrier (plcc) 64-pin quad flat pack (qfp) the following figures show the latest pac kage drawings at the time of this publication. to make sure that you have the latest package specifications, contact your local freescale sales office 18.2 mc order numbers these part numbers are generic numbers only. to place an order, rom code must be submitted to the rom processing center (rpc). figure 18-1. device numbering system table 18-1. mc order numbers mc order number operating temperature range mc68hc08as32fn (1) 1. fn = plastic leaded chip carrier 0 c to + 70 c mc68hc08as32cfn ?40 c to + 85 c MC68HC08AS32VFN ?40 c to + 105 c mc68hc08as32fu (2) 2. fu = quad flat pack 0 c to + 70 c mc68hc08as32cfu ?40 c to + 85 c mc68hc08as32vfu ?40 c to + 105 c m c 6 8 h c 0 8 a s 3 2 x x x family package designator temperature range
data sheet mc68hc08as32 ? rev. 4.1 276 freescale semiconductor 18.3 52-pin plasti c leaded chip carrier package (case 778) ?l? y brk w d d v 52 1 notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t?, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). b u z g1 x view d?d h k1 k f view s m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n 0.004 (0.100) ?t? seating plane m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n a r g g1 c z j e view s ?m? ?n? dim min max min max millimeters inches a 0.785 0.795 19.94 20.19 b 0.785 0.795 19.94 20.19 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 ??? 0.51 ??? k 0.025 ??? 0.64 ??? r 0.750 0.756 19.05 19.20 u 0.750 0.756 19.05 19.20 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y ??? 0.020 ??? 0.50 z 2 10 2 10 g1 0.710 0.730 18.04 18.54 k1 0.040 ??? 1.02 ??? m 0.007 (0.18) l?m s t s n m 0.007 (0.18) l?m s t s n s 0.010 (0.25) l?m s t s n s 0.010 (0.25) l?m s t s n
mc68hc08as32 ? rev. 4.1 data sheet freescale semiconductor 277 18.4 64-pin quad flat pack (case 840b) l l ?a? ?b? detail a ?d? b a s v detail a p b b d ?a?, ?b?, ?d? c ?c? e h g m m detailc seating plane datum plane 1 16 ?h? 0.01 (0.004) r detail c datum plane ?h? t u q k w x s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h 48 33 s a?b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ??? 0.25 ??? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ??? 0.005 ??? u 0 ??? 0 ??? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 0.10 (0.004) c h h d c 0.20 (0.008) section b-b
data sheet mc68hc08as32 ? rev. 4.1 278 freescale semiconductor

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